Abstract: An adaptive thermal control system maintains and regulates an accurate and stable thermal environment for a device under test. The adaptive thermal control system includes (i) pre-trigger communications from automatic test equipment (ATE) to automatic thermal control (ATC) allowing slow-responding ATC to start responding to an imminent thermal change before the thermal change occurs, (ii) a control profile which indicates to the ATC, prior to anticipated thermal change, that a change is imminent and the nature of the change over time. The generation and fine-tuning of the control profile can be done by two different methods (i) with the semi-automatic approach the tester does some pre-tests in order to determine a typical response profile which the test program then adjusts using adaptive techniques, (ii) With the fully automatic adaptive circuitries same typical response profile is algorithmically adjusted and utilized to control the ATC.

Abstract: An adaptive thermal control system maintains and regulates an accurate and stable thermal environment for a device under test. The adaptive thermal control system includes (i) pre-trigger communications from automatic test equipment (ATE) to automatic thermal control (ATC) allowing slow-responding ATC to start responding to an imminent thermal change before the thermal change occurs, (ii) a control profile which indicates to the ATC, prior to anticipated thermal change, that a change is imminent and the nature of the change over time. The generation and fine-tuning of the control profile can be done by two different methods (i) with the semi-automatic approach the tester does some pre-tests in order to determine a typical response profile which the test program then adjusts using adaptive techniques, (ii) With the fully automatic adaptive circuitries same typical response profile is algorithmically adjusted and utilized to control the ATC.

Abstract: An integrated circuit, including a configurable scan architecture used for an integrated circuit test procedure and quality control. The configurable scan chain architecture has the capability of being reconfigured to one of a variety scan chain architectures based on the constraints of the integrated circuit and the testing device. The present invention minimizes the integrated circuit test time by reconfiguring the scan architecture depending on certain constraints such as the latching frequency, the predetermined I/O frequency, the number of available integrated circuit I/O pins, the number of pins required for a proposed scan architecture, and the number of available pins on the testing device. The configurable scan architecture receives configuration signals which indicate which scan chain architecture should be configured on the integrated circuit that is being tested.

Abstract: An integrated circuit, including a configurable scan architecture used for an integrated circuit test procedure and quality control. The configurable scan chain architecture has the capability of being reconfigured to one of a variety scan chain architectures based on the constraints of the integrated circuit and the testing device. The present invention minimizes the integrated circuit test time by reconfiguring the scan architecture depending on certain constraints such as the latching frequency, the predetermined I/O frequency, the number of available integrated circuit I/O pins, the number of pins required for a proposed scan architecture, and the number of available pins on the testing device. The configurable scan architecture receives configuration signals which indicate which scan chain architecture should be configured on the integrated circuit that is being tested.

Abstract: An apparatus and method are provided for testing component tolerances of a device for testing integrated circuits. The testing device is generally characterized by a plurality of test connectors disposed at a test head, wherein each test connector carries electrical signals for a test channel. Further, each test channel generally corresponds to a circuit board that includes at least one driver and one receiver. In this general type of tester, a system is provided that includes a specialized DUT board that establishes a low impedance electrical connection (i.e., short) between electrical conductors of a first and second test connector. Through this low impedance path, a first driver from a first circuit board is directly connected (i.e., shorted) to a first receiver on a second circuit board. A controller is configured to control the first driver to output an electrical signal at a predetermined time.