Patents by Inventor David H. Armstrong

David H. Armstrong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210271272
    Abstract: A plural component dispensing system includes a dispensing device, first and second fluid component sources, a system controller, and an operator interface device. The first fluid component source is connected to the dispensing device to deliver the first fluid component to the dispensing device. The second fluid component source is connected to the dispensing device to deliver the second fluid component to the dispensing device. The system controller is connected to regulate operation of the first fluid component source and the second fluid component source to produce a target ratio of the first fluid component and the second fluid component at the dispensing device. The operator interface device is remote from and operatively connected to the system controller. The operator interface device is configured to output system state information received from the system controller and to receive operator input to control an operational state of the system controller.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Thomas V. Vo, Jeffrey S. Armstrong, David Bordwell, Jonathan R. McMichael, Christopher M. Lange, Nicholas A. Pagano, Benjamin R. Godding, Mark T. Weinberger, Michael J. Manshiem, Andrew J. Kopel, Nicholas H. Reath
  • Patent number: 9291667
    Abstract: An adaptive thermal control system maintains and regulates an accurate and stable thermal environment for a device under test. The adaptive thermal control system includes (i) pre-trigger communications from automatic test equipment (ATE) to automatic thermal control (ATC) allowing slow-responding ATC to start responding to an imminent thermal change before the thermal change occurs, (ii) a control profile which indicates to the ATC, prior to anticipated thermal change, that a change is imminent and the nature of the change over time. The generation and fine-tuning of the control profile can be done by two different methods (i) with the semi-automatic approach the tester does some pre-tests in order to determine a typical response profile which the test program then adjusts using adaptive techniques, (ii) With the fully automatic adaptive circuitries same typical response profile is algorithmically adjusted and utilized to control the ATC.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 22, 2016
    Assignee: ADVANTEST CORPORATION
    Inventors: David H. Armstrong, Mike Callaway
  • Publication number: 20140253155
    Abstract: An adaptive thermal control system maintains and regulates an accurate and stable thermal environment for a device under test. The adaptive thermal control system includes (i) pre-trigger communications from automatic test equipment (ATE) to automatic thermal control (ATC) allowing slow-responding ATC to start responding to an imminent thermal change before the thermal change occurs, (ii) a control profile which indicates to the ATC, prior to anticipated thermal change, that a change is imminent and the nature of the change over time. The generation and fine-tuning of the control profile can be done by two different methods (i) with the semi-automatic approach the tester does some pre-tests in order to determine a typical response profile which the test program then adjusts using adaptive techniques, (ii) With the fully automatic adaptive circuitries same typical response profile is algorithmically adjusted and utilized to control the ATC.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 11, 2014
    Applicant: Advantest Corporation
    Inventors: David H. ARMSTRONG, Mike CALLAWAY
  • Patent number: 7137053
    Abstract: An integrated circuit, including a configurable scan architecture used for an integrated circuit test procedure and quality control. The configurable scan chain architecture has the capability of being reconfigured to one of a variety scan chain architectures based on the constraints of the integrated circuit and the testing device. The present invention minimizes the integrated circuit test time by reconfiguring the scan architecture depending on certain constraints such as the latching frequency, the predetermined I/O frequency, the number of available integrated circuit I/O pins, the number of pins required for a proposed scan architecture, and the number of available pins on the testing device. The configurable scan architecture receives configuration signals which indicate which scan chain architecture should be configured on the integrated circuit that is being tested.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: November 14, 2006
    Assignee: Verigg IPco
    Inventors: Ajay Khoche, Jochen Rivoir, David H. Armstrong
  • Publication number: 20030046623
    Abstract: An integrated circuit, including a configurable scan architecture used for an integrated circuit test procedure and quality control. The configurable scan chain architecture has the capability of being reconfigured to one of a variety scan chain architectures based on the constraints of the integrated circuit and the testing device. The present invention minimizes the integrated circuit test time by reconfiguring the scan architecture depending on certain constraints such as the latching frequency, the predetermined I/O frequency, the number of available integrated circuit I/O pins, the number of pins required for a proposed scan architecture, and the number of available pins on the testing device. The configurable scan architecture receives configuration signals which indicate which scan chain architecture should be configured on the integrated circuit that is being tested.
    Type: Application
    Filed: September 4, 2001
    Publication date: March 6, 2003
    Inventors: Ajay Khoche, Jochen Rivoir, David H. Armstrong
  • Patent number: 6192496
    Abstract: An apparatus and method are provided for testing component tolerances of a device for testing integrated circuits. The testing device is generally characterized by a plurality of test connectors disposed at a test head, wherein each test connector carries electrical signals for a test channel. Further, each test channel generally corresponds to a circuit board that includes at least one driver and one receiver. In this general type of tester, a system is provided that includes a specialized DUT board that establishes a low impedance electrical connection (i.e., short) between electrical conductors of a first and second test connector. Through this low impedance path, a first driver from a first circuit board is directly connected (i.e., shorted) to a first receiver on a second circuit board. A controller is configured to control the first driver to output an electrical signal at a predetermined time.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: February 20, 2001
    Assignee: Agilent Technologies, Inc.
    Inventors: William R. Lawrence, David H. Armstrong