Abstract: An on chip monitoring circuit is disclosed which enables the rapid characterization of signal propagation speed for integrated circuits on the same chip. The circuit is based upon a correlation between signal propagation speed on the chip and the low pass filtering characteristics of the monitoring circuit, which is a classical first order low pass filter. The monitoring circuit performs the low pass filter operation from which the operator can determine what the signal propagation characteristics are for other integrated circuits on the chip resulting from specific process parameters which occurred during the fabrication of the chip. A feature of the invention is its ability to characterize very small capacitive and resistive contributions to signal propagation delay by using input driving frequencies which are moderately low, by using the principle of the Miller Theorem.

Abstract: An M-bit binary counter is disclosed having M sequentially ascending binary value stages, the first stage being the lowest significant bit. In accordance with the invention, each stage above the least significant bit stage has a subsequent value decoder which has the function of determining the effect of lower order carry bits on higher order stages with a minimum of signal delay. The decoder includes the feature of using natural threshold FET devices in a transfer gate configuration to perform logical AND functions so as to minimize gate delays in decoding a carry condition for higher order stages. A selective up-counting or down-counting function is also disclosed.

Abstract: A "natural" threshold device is serially connected between the gate of an output depletion mode FET device and the input node to an FET device so as to provide current flow from the input node to the gate of the FET device as the input waveform begins to rise, and yet to provide sufficient resistance in the gate circuit of the depletion mode device so as to prevent backward flow of current from the gate as the potential of the output node rises. This increases the conductivity of the output load device, thereby providing a faster rise time for the output waveform.

Abstract: A low capacitance pad structure is disclosed for testing a semiconductor chip, so as to enable the accurate measurement of rise times and delays in internal logic circuitry. The structure provides a capacitive coupling between the internal logic circuit under test and the capacitance of the probe connected to the input/output pad of the chip. This is achieved by inserting a coupling capacitance between the internal logic circuit and the input/output pad. The coupling capacitance is formed by providing a thin dielectric layer on top of an enlarged plate portion of the conductor line connected to the output of the internal logic circuit under test, so as to capacitively couple voltage swings on the line to a second level plate which forms the electrode to be contacted by the test probe.