Abstract: A customizable circuit using a programmable interconnect and compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form long diagonal lines having a pitch determined by the basic wire segment length. Uniform capacitance effects are achieved by alternating the layers of the wire segments. The terminal ends of the segments are positioned in a plane such that segments may be connected by short links to form the desired interconnect. The links which join the line segments customize the otherwise undedicated interconnect. Resistive links may be used to minimize undesirable transmission line effects. The segment ends may also be connected through electrically programmable elements. Carrier tape bonds the integrated circuit chips to the programmable interconnect.

Abstract: An peripheral to area adapter for an integrated circuit chip. The adapter comprises pads on an upper surface of a support in a pattern corresponding to the terminals on a integrated circuit, planar reroute lines on the upper surface with first ends at the pads, and vertical conductive vias extending through the support. The vias are connected at the upper surface to the second ends of the reroute lines. The vias are connected at the lower surface of the support to an area array of coupling elements. The pads and reroute lines can be fabricated on a tape-automated-bonding (TAB) frame support and personalized to match a particular configuration of terminals or bumps on a chip. The coupling elements can form a generic array compatible with a wide variety of interconnect substrates.

Abstract: An peripheral to area adapter for an integrated circuit chip. The adapter comprises pads on an upper surface of a support in a pattern corresponding to the terminals on a integrated circuit, planar reroute lines on the upper surface with first ends at the pads, and vertical conductive vias extending through the support. The vias are connected at the upper surface to the second ends of the reroute lines. The vias are connected at the lower surface of the support to an area array of coupling elements. A protective bumper attached to the sides of the package provides mechanical shielding for the chip. The pads and reroute lines can be fabricated on a tape-automated-bonding (TAB) frame support and personalized to match a particular configuration of terminals or bumps on a chip. The coupling elements can form a generic array compatible with a wide variety of interconnect substrates.

Abstract: A process for producing fine pitch surface features on a multilayer printed circuit boards such as copper-polyimide interconnects without requiring a thick copper plating foil. Initially, a thin first conductor (less than 1 micron) is vacuum deposited on a dielectric base and the dielectric base is disposed on a substrate. The substrate is then laminated and through-holes are formed therethrough. A plating seed is deposited in the through-holes and resist is patterned on the first conductor. A second conductor is deposited on the exposed portions of the first conductor and on the sidewalls, the resist is stripped and the portions or the first conductor beneath the resist are removed using a brief wet chemical etch to form spaced features without significant undercut. In the preferred embodiment, vacuum deposition occurs in a continuous roll sputtering system.

Abstract: The invention relates to an electrical interconnect device with power and ground lines interwoven about signal line layers and capacitive vias between signal layers so as to make efficient use of otherwise undedicated area between signal lines and signal layers and to reduce or eliminate the need for separate power and ground layers while providing decoupling capacitance within the wiring structure.

Abstract: A method of forming recessed patterns in insulators is described. One embodiment of the invention is directed to ceramic green sheet fabrication by providing a sculptured plastic tape mold which includes a floor, a plurality of sidewalls adjacent to and extending above the floor and a plurality of protrusions on and extending above the floor, casting a ceramic slurry into the mold such that the slurry contacts the floor, the sidewalls and the protrusions, and drying the slurry so as to produce a ceramic green sheet with a recessed pattern that replicates the shapes of the protrusions. The ceramic green sheet may be removed from the mold and filled with a conductor before firing; alternatively, the ceramic green sheet can be fired before removing the mold to form a rigid ceramic substrate which is then filled with a conductor.

Abstract: Trenching techniques for forming a channel partially through and a via completely through the insulating layer of a substrate are disclosed. With additional steps the channel can form an electrically conductive line, an electrode of an integrated capacitor, or an optical waveguide.

Abstract: Removing welded outer lead bonds of TAB tape leads to contacts on a substrate. The method includes separating the electrical leads adjacent the weld bonds leaving a remnant, engaging the remnant with a shear tool, and moving the tool and bond relative to each other shearing the remnant. In some cases the tool is ultrasonically vibrated in a direction transversely to the relative movement of the tool and bond.

Abstract: Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias.

Abstract: A customizable circuit using a programmable interconnect and a compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form along diagonal lines having a pitch determined by the basic wire segment length. The terminal ends of each of these segments are positioned in a plane such that the segments may be connected by short lengths to form the desired interconnect. The links which join the line segments represent the customization of the otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the integrated circuit chips to the programmable interconnect. Also disclosed are methods for forming the interconnect and the TAB chip bonding design.

Abstract: A customizable circuit using a programmable interconnect and a compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form along diagonal lines having a pitch determined by the basic wire segment length. The terminal ends of each of these segments are positioned in a plane such that the segments may be connected by short lengths to form the desired interconnect. The links which join the line segments represent the customization of the otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the intergrated circuit chips to the programmable interconnect. Also disclosed are methods for forming the interconnect and the TAB chip bonding design.

Abstract: A method of making a metal-on-elastomer pressure contact connector. The method includes embedding a plurality of parallel co-planar copper-beryllia wires comprising a plurality of coils in a silicone rubber elastomer with top and bottom surfaces, and removing metal from the tops and bottoms of the coils to form a pair of isolated wire filaments from each coil which extend from the top surface to the bottom surface of the elastomer. The filaments form arrays of electrical contacts above and below the elastomer exceeding 10,000 contacts per square inch.

Abstract: Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias.

Abstract: A capacitor, having an area smaller than the top area of a chip, is attached above the top of a tape-automated-bonded (TAB) chip and short bonded wires or TAB leads interconnect the capacitor electrodes with the power and ground pads on the chip. The interconnections are made as short as possible, with a maximum distance therebetween and with the greatest number which will reduce the inductance of the leads. The power and ground pads may contain inwardly extending bonding regions for wire bonds or flip chip capacitor attachment.

Abstract: A substrate for attaching electrical devices having an interconnect wiring structure and a support for the interconnect, the support having a number of vias, or throughholes, extending therethrough and electrically connected to the interconnect. The substrate allows for attachment of the electrical devices on the side of the support opposite the interconnect at the vias, rather than on the interconnect itself. By so doing, the chips can be packed more density since the area between the chips normally reserved for engineering change pads, test pads and the like is not required, these functions being performed on the interconnect on the opposite side of the substrate.

Abstract: A substrate for attaching electrical devices having an interconnect wiring structure and a support for the interconnect, the support having a number of vias, or throughholes, extending therethrough and electrically connected to the interconnect. The substrate allows for attachment of the electrical devices on the side of the support opposite the interconnect at the vias, rather than on the interconnect itself. By so doing, the chips can be packed more densely since the area between the chips normally reserved for engineering change pads, test pads and the like is not required, these functions being performed on the interconnect on the opposite side of the substrate.

Abstract: A multigigahertz probe for testing electrical micro connections or wafers. A body has a top, bottom and a testing tip at one end, and the one end slants upwardly and inwardly from the bottom towards the top. At least one coaxial cable is carried by the body and includes a first connector end and a second testing end forming testing contacts. The testing end extends to the intersection of the bottom and the slanting one end of the body.