Patents by Inventor David H. Chow

David H. Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11314109
    Abstract: A spatial light modulator cell and arrays of spatial light modulator cells are disclosed. The spatial light modulator cells can comprise a phase change material (PCM) having a first side and a second side; an optical reflector configured to reflect an optical beam passing from the first side to the second side; and a PCM heater thermal conductively coupled to the PCM, wherein thermal modulation of the PCM modulates a phase of the PCM which varies light transmission through the PCM. Methods of making spatial light modulator cells and arrays are also disclosed.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 26, 2022
    Assignee: URL Laboratories, LLC
    Inventors: Jeong-Sun Moon, Adour V. Kabakian, David H. Chow, Richard M. Kremer
  • Patent number: 11302739
    Abstract: An infrared detector. The detector includes: a superlattice structure including: at least three first layers; and at least three second layers, alternating with the first layers. Each of the first layers includes, as a major component, InAsxP1-x, wherein x is between 0.0% and 99.0%, and each of the second layers includes, as a major component, InAsySb1-y, wherein y is between 0% and 60%.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: April 12, 2022
    Assignee: HRL Laboratories, LLC
    Inventors: Minh B. Nguyen, Rajesh D. Rajavel, David H. Chow
  • Patent number: 8957455
    Abstract: A heterojunction bipolar transistor (HBT) having an emitter, a base, and a collector, the base including a first semiconductor layer coupled to the collector, the first semiconductor layer having a first bandgap between a first conduction band and a first valence band and a second semiconductor layer coupled to the first semiconductor layer and having a second bandgap between a second conduction band and a second valence band, wherein the second valence band is higher than the first valence band and wherein the second semiconductor layer comprises a two dimensional hole gas and a third semiconductor layer coupled to the second semiconductor layer and having a third bandgap between a third conduction band and a third valence band, wherein the third valence band is lower than the second valence band and wherein the third semiconductor layer is coupled to the emitter.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: February 17, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: James Chingwei Li, Marko Sokolich, Tahir Hussain, David H. Chow
  • Patent number: 8178946
    Abstract: A heterojunction bipolar transistor (HBT) having an emitter, a base, and a collector, the base including a first semiconductor layer coupled to the collector, the first semiconductor layer having a first bandgap between a first conduction band and a first valence band and a second semiconductor layer coupled to the first semiconductor layer and having a second bandgap between a second conduction band and a second valence band, wherein the second valence band is higher than the first valence band and wherein the second semiconductor layer comprises a two dimensional hole gas and a third semiconductor layer coupled to the second semiconductor layer and having a third bandgap between a third conduction band and a third valence band, wherein the third valence band is lower than the second valence band and wherein the third semiconductor layer is coupled to the emitter.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: May 15, 2012
    Assignee: HRL Laboratories, LLC
    Inventors: James Chingwei Li, Marko Sokolich, Tahir Hussain, David H. Chow
  • Patent number: 7868335
    Abstract: A bipolar junction transistor having an emitter, a base, and a collector includes a stack of one or more layer sets adjacent the collector. Each layer set includes a first material having a first band gap, wherein the first material is highly doped, and a second material having a second band gap narrower than the first band gap, wherein the second material is at most lightly doped.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: January 11, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: James Chingwei Li, Marko Sokolich, Tahir Hussain, David H. Chow
  • Patent number: 7800067
    Abstract: Electronically tunable and reconfigurable hyperspectral IR detectors and methods for making the same are presented. In one embodiment, a reconfigurable hyperspectral sensor (or detector) detects radiation from about 0.4 ?m to about 2 ?m and beyond. This sensor is configured to be compact, and lightweight and offers hyperspectral imaging capability while providing wavelength agility and tunability at the chip-level. That is, the sensor is used to rapidly image across diverse terrain to identify man-made objects and other anomalies in cluttered environments.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: September 21, 2010
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, David H. Chow, Andrew T. Hunter
  • Patent number: 7755023
    Abstract: Electronically tunable and reconfigurable hyperspectral IR detectors and methods for making the same are presented. In one embodiment, a reconfigurable hyperspectral sensor (or detector) detects radiation from about 0.4 ?m to about 2 ?m and beyond. This sensor is configured to be compact, and lightweight and offers hyperspectral imaging capability while providing wavelength agility and tunability at the chip-level. That is, the sensor is used to rapidly image across diverse terrain to identify man-made objects and other anomalies in cluttered environments.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: July 13, 2010
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, David H. Chow, Andrew T. Hunter
  • Patent number: 7700969
    Abstract: A semiconductor device exhibiting interband tunneling with a first layer with a first conduction band edge with an energy above a first valence band edge, with the difference a first band-gap. A second layer with second conduction band edge with an energy above a second valence band edge, with the difference a second band-gap, and the second layer formed permitting electron carrier tunneling transport. The second layer is between the first and a third layer, with the difference between the third valence band edge and the third conduction band edge a third band-gap. A Fermi level is nearer the first conduction band edge than the first valence band edge. The second valence band edge is beneath the first conduction band edge. The second conduction band edge is above the third valence band edge. The Fermi level is nearer the third valence band edge than to the third conduction band edge.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: April 20, 2010
    Assignee: HRL Laboratories, LLC
    Inventors: Joel N. Schulman, David H. Chow, Chanh Nguyen
  • Patent number: 7652252
    Abstract: Electronically tunable and reconfigurable hyperspectral IR detectors and methods for making the same are presented. In one embodiment, a reconfigurable hyperspectral sensor (or detector) detects radiation from about 0.4 ?m to about 2 ?m and beyond. This sensor is configured to be compact, and lightweight and offers hyperspectral imaging capability while providing wavelength agility and tunability at the chip-level. That is, the sensor is used to rapidly image across diverse terrain to identify man-made objects and other anomalies in cluttered environments.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: January 26, 2010
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, David H. Chow, Andrew T. Hunter
  • Patent number: 7582536
    Abstract: An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: September 1, 2009
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, Mary Y. Chen, Steven S. Bui, David H. Chow, James Chingwei Li, Mehran Mokhtari, Marko Sokolich
  • Patent number: 7569872
    Abstract: Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: August 4, 2009
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, David H. Chow, Tahir Hussain, Yakov Royter
  • Patent number: 7531851
    Abstract: An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: May 12, 2009
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, Mary Y. Chen, Steven S. Bui, David H. Chow, James Chingwei Li, Mehran Mokhtari, Marko Sokolich
  • Patent number: 7514708
    Abstract: A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyimide passivation and planarization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substrate 100 that serves as a foundation for bottom contact layers 102 and a polyimide 700 coating. An ohmic metal contact 300 and emitter metal contact 400 protrude above the polyimide 700 coating exposing the ohmic metal contact 300 and emitter metal contact 400. The contacts are capped with an etch-resistant coating 710 thus allowing for the polyimide etch, and other etching processes without adversely affecting the contacts.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: April 7, 2009
    Assignee: HRL Laboratories, LLC
    Inventors: Stephen Thomas, III, Ken Elliott, David H. Chow
  • Patent number: 7372084
    Abstract: Low power double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: May 13, 2008
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, Kenneth Elliott, David H. Chow
  • Patent number: 7368765
    Abstract: Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: May 6, 2008
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, David H. Chow, Tahir Hussain, Yakov Royter
  • Patent number: 7170105
    Abstract: A semiconductor device exhibiting interband tunneling with a first layer with a first conduction band edge with an energy above a first valence band edge, with the difference a first band-gap. A second layer with second conduction band edge with an energy above a second valence band edge, with the difference a second band-gap, and the second layer formed permitting electron carrier tunneling transport. The second layer is between the first and a third layer, with the difference between the third valence band edge and the third conduction band edge a third band-gap. A Fermi level is nearer the first conduction band edge than the first valence band edge. The second valence band edge is beneath the first conduction band edge. The second conduction band edge is above the third valence band edge. The Fermi level is nearer the third valence band edge than to the third conduction band edge.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: January 30, 2007
    Assignee: HRL Laboratories, LLC
    Inventors: Joel N. Schulman, David H. Chow, Chanh Nguyen
  • Patent number: 6812070
    Abstract: A method of epitaxially growing backward diodes and diodes grown by the method are presented herein. More specifically, the invention utilizes epitaxial-growth techniques such as molecular beam epitaxy in order to produce a thin, highly doped layer at the p-n junction in order to steepen the voltage drop at the junction, and thereby increase the electric field. By tailoring the p and n doping levels as well as adjusting the thin, highly doped layer, backward diodes may be consistently produced and may be tailored in a relatively easy and controllable fashion for a variety of applications. The use of the thin, highly doped layer provided by the present invention is discussed particularly in the context of InGaAs backward diode structures, but may be tailored to many diode types.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: November 2, 2004
    Assignee: HRL Laboratories, LLC
    Inventors: Joel N. Schulman, David H. Chow
  • Patent number: 6734470
    Abstract: A method for producing laterally varying multiple diodes and their device embodiment are presented herein. As demonstrated, multiple resonant tunneling diodes are fabricated together utilizing a single epitaxial structure. Shallow, ion-implanted regions having varying depths, dx, define the collector contacts. Each diode is isolated electrically from the others by methods such as conventional mesa etching into the emitter layer. The varying depths, dx, provide means for varying the peak voltage of each individual diode. The peak voltage strongly depends on the depths, dx, because it comprises a space charge region where the electric field is high, and therefore the voltage drop is high. The invention disclosed herein is useful in applications such as high-speed circuits such as comparators, analog to digital converters, sample and hold circuits, logic devices, and frequency multipliers.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: May 11, 2004
    Assignee: HRL Laboratories, LLC
    Inventors: Joel N. Schulman, David H. Chow
  • Patent number: 6727153
    Abstract: A semiconductor structure and a method of forming same is disclosed. The method includes forming, on a substrate, an n-doped collector structure of InAs/AlSb materials; forming a base structure on said collector structure which base structure comprises p-doped GaSb; and forming, on said base structure, an n-doped emitter structure of InAs/AlSb materials. The collector and emitter structure are preferably superlattices each comprising a plurality of periods of InAs and AlSb sublayers. A heterojunction bipolar transistor manufactured using the method is disclosed.
    Type: Grant
    Filed: September 7, 2001
    Date of Patent: April 27, 2004
    Assignee: HRL Laboratories, LLC
    Inventor: David H. Chow
  • Publication number: 20030230759
    Abstract: A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyimide passivation and planarization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substrate 100 that serves as a foundation for bottom contact layers 102 and a polyimide 700 coating. An ohmic metal contact 300 and emitter metal contact 400 protrude above the polyimide 700 coating exposing the ohmic metal contact 300 and emitter metal contact 400. The contacts are capped with an etch-resistant coating 710 thus allowing for the polyimide etch, and other etching processes without adversely affecting the contacts.
    Type: Application
    Filed: April 22, 2003
    Publication date: December 18, 2003
    Inventors: Stephen Thomas, Ken Elliott, David H. Chow