Abstract: A processing system comprising: i) a read-only memory (ROM) that stores original ROM code; ii) a custom array that stores replacement ROM code; and iii) control logic that receives an incoming ROM address and a read request signal generated by a source device. The control logic, in response to receipt of the incoming ROM address and the read request signal, compares the incoming ROM address to a patched address associated with the ROM. If a match occurs, the control logic outputs to the custom array a translated address associated with the patched address. The custom array then outputs a first line of replacement ROM code associated with the translated address.

Abstract: A full swing CMOS output buffer circuit (20,30,40,50) isolates incompatible power supply circuits such as 3.3 v standard and 5 v standard subcircuits, and isolates power supply rails of quiet or powered down buffer circuits from the common external bus. The pullup output transistor (PMOS1) is fabricated in a well (NWELL) of N type carrier semiconductor material formed in a substrate (PSUB) of P type carrier semiconductor material. A P channel NWELL isolation switch transistor (PW1) has a primary current path coupled between the well (NWELL) and high potential power rail (VCC) and a control gate node coupled to the control gate node of the pullup output transistor (PMOS1) for operating substantially in phase. The NWELL isolation switch transistor (PW1) isolates the pullup output transistor (PMOS1) well (NWELL) from the high potential power rail (VCC).