Abstract: A system for developing a simulation of a process. In one aspect, a system creates a first model within the simulation. The first model represents a part of the process and comprises a first port to which other models may be connected. The system also creates a second model within the simulation. The second model represents another part of the process and comprises a second port to which other models may be connected. The system then connects the first port and the second port together. Upon connection, the system allocates a memory location as a connection variable that represents a type of information transfer between the first and second ports. A first port variable, which represents a value transferrable through the first port, is set to reference the value at the allocated memory location. Similarly, a second port variable, which represents a value transferrable through the second port, is also set to reference the value at the allocated memory location.

Abstract: A method and system for prefetching sound data in a sound processor system. The method includes integrating a prefetching function into at least one voice engine by, providing a setup phase, a data processing phase, and a cleanup phase, and prefetching sound data from a memory during the cleanup phase. As a result, the prefetching of sound data is optimized.

Abstract: The present invention provides a method and system for reducing power consumption of a sound processor. Aspects of the invention include providing a sound processor access to at least one register having a plurality of bits corresponding to sound operations capable of being performed by the sound processor; and allowing a host processor to write a value to at least a portion of the plurality of bits in the register during sound processing to selectively disable individual operations performed by the sound processor.

Abstract: A system and method for controlling access to parameter blocks of a sound processor. According to the method and system disclosed herein, the present invention includes a host, a sound processor coupled to the host, and at least two copies of a parameter block associated with the sound data. The sound processor can access a first copy of the at least two copies while the host is accessing a second copy of the at least two copies. As a result, parameter blocks are freely updated by the host processor and freely read by the sound processor without conflict and without performance loss.

Abstract: A system and method for implementing a sound processor. The sound processor includes a first voice engine, a second voice engine, and at least one single-port memory unit. An operation of the first voice engine and an operation of the second voice engine are time offset, wherein the time offset enables the first and second voice engines to share the at least one memory unit without contention. This results in cost savings and power consumption savings due to the smaller area needed for the memories.

Abstract: An apparatus comprising a plurality of flip-flops and a compare circuit. The flip-flops may each be configured to (i) receive a clock signal and an input signal and (ii) generate an output signal. The flip-flops may be configured in series such that the output signal of a first of the flip-flops is presented as the input signal to a second of the flip-flops. The compare circuit may be configured to generate a reset signal in response to each of the output signals. The reset signal is generated until each of the output signals matches a set of predetermined values stored in the compare circuit.

Abstract: An apparatus comprising a plurality of flip-flops and a compare circuit. The flip-flops may each be configured to (i) receive a clock signal and an input signal and (ii) generate an output signal. The flip-flops may be configured in series such that the output signal of a first of the flip-flops is presented as the input signal to a second of the flip-flops. The compare circuit may be configured to generate a reset signal in response to each of the output signals. The reset signal is generated until each of the output signals matches a set of predetermined values stored in the compare circuit.

Abstract: For use in a floating-point unit that supports floating-point formats having fractional parts of varying widths and employs a datapath wider than the fractional parts, a circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method. In one embodiment, the circuit includes: (1) left-shift circuitry for aligning a fractional part of the floating-point result with a most significant bit of the datapath and irrespective of a width of the fractional part to yield a shifted fractional part and (2) rounding circuitry, coupled to the shift circuitry, that rounds the shifted fractional part.

Abstract: Packet routing method and system that routes packets to one of at least two processes based on at least one routing rule for processing packets from network traffic. First, at least one routing rule is received. The routing rule specifies one or more packet criteria (e.g., network card through which the packet is received or a predetermined source address of the packet). The routing rule also specifies a predetermined route or path for packets that meet the criteria described previously. Second, packets are received from a source (e.g., network traffic). Third, the routing rule is applied to the received packets. When the packet matches the criteria, the packet is routed to a predetermined process (e.g., a first application) through a corresponding route or path. The predetermined process then performs further packet processing on the routed packet. Otherwise, the packet is routed to a predetermined process (e.g., a second application) through a predetermined route.

Abstract: A channel time-out apparatus in a data processing system having a channel processor for controlling the allocation of a plurality of input/output channels. The channel time-out apparatus comprises a clock for generating time indications, an address generator for generating an address for each input/output channel of the plurality of input/output channels, a time-out generator for generating a time-out indicator for an input/output channel whenever that input/output channel processes an instruction, storage for storing the last time-out indicator generated by the time-out means for each input/output channel and a comparator for comparing the last time-out indicator stored in the storage for the input/output channel whose address is presently being generated by the address generator with a time indicator presently being generated by the clock for determining when a time-out event has occurred without requiring intervention by the processor.

Abstract: An apparatus and method for processing channel time-out for input/output channels in a data processing system. A counting device is provided which cycles through a count indicative, in a first part, of each of a plurality of channels in the data processing system and, in a second part, a sequence of time indications. A time indication is saved for a particular channel upon the execution of an instruction for that channel and subsequent comparisons are made of the stored time indication and the present time indication to determine if a difference in these two time indications is sufficient to constitute a time-out.