Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

Abstract: A semiconductor package for skew matching in a die-to-die interface, including: a first die; a second die aligned with the first die such that each connection point of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die; and a plurality of connection paths of a substantially same length, wherein each connection path of the plurality of connection paths couples a respective connection point of the first plurality of connection points to the corresponding connection point of the second plurality of connection points.

Abstract: A dynamic NOR circuit includes a pre-charge transistor coupled between a first voltage supply node and a dynamic node to pre-charge the dynamic node. The dynamic NOR circuit includes a first keeper circuit having a first keeper transistor and a second keeper transistor serially coupled between the first voltage supply node and the dynamic node. The dynamic NOR circuit includes a first pull down circuit coupled between the dynamic node and ground. A first input signal is coupled to a gate of a first pull-down transistor in the first pull-down circuit and is also coupled to a gate of the first keeper transistor. A first keeper enable signal is coupled to a gate of the second keeper transistor. Additional keeper circuits and pull down circuits coupled to the dynamic node allow the dynamic NOR structure to handle a plurality of input signals.

Abstract: A dynamic NOR circuit includes a pre-charge transistor coupled between a first voltage supply node and a dynamic node to pre-charge the dynamic node. The dynamic NOR circuit includes a first keeper circuit having a first keeper transistor and a second keeper transistor serially coupled between the first voltage supply node and the dynamic node. The dynamic NOR circuit includes a first pull down circuit coupled between the dynamic node and ground. A first input signal is coupled to a gate of a first pull-down transistor in the first pull-down circuit and is also coupled to a gate of the first keeper transistor. A first keeper enable signal is coupled to a gate of the second keeper transistor. Additional keeper circuits and pull down circuits coupled to the dynamic node allow the dynamic NOR structure to handle a plurality of input signals.

Abstract: Methods and apparatuses are disclosed for measuring values of a plurality of memory elements, where the measured values may be indicative of the digital state of a memory element. Calculations may be performed on a plurality of transition-terms associated with the possible transitions in the values between proximate memory elements. The digital state of memory elements may be determined using the calculations performed on the plurality of transition-terms.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells 16 of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols 206 in a block of ECC encoded data 204 which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells 16. Where the position of suspected failed symbols 206 is known from this erasure information, the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

Abstract: Methods and apparatuses are disclosed for measuring values of a plurality of memory elements, where the measured values may be indicative of the digital state of a memory element. Calculations may be performed on a plurality of transition-terms associated with the possible transitions in the values between proximate memory elements. The digital state of memory elements may be determined using the calculations performed on the plurality of transition-terms.

Abstract: A magnetic random access memory array includes a data storage layer having an easy axis. A non-linear first conductor is positioned on a first side of the data storage layer, wherein a portion of the first conductor has an angle of orientation that is perpendicular to the easy axis. A non-linear second conductor is positioned on a second side of the data storage layer, wherein a portion of the second conductor also has an angle of orientation that is perpendicular to the easy axis.

Abstract: Systems and methods for reducing the effect of noise while reading data in series from memory, are provided. One system embodiment comprises a memory cell that stores a first data; a sensing device that receives the first data multiple times and provides a first set of outputs; and a voting system that evaluates the first set of outputs to determine whether one of the outputs of the first set is valid data from the memory cell. One method embodiment comprises reading data in series that is stored in a memory cell to provide outputs; and evaluating the outputs to determine whether one of the outputs is valid data from the memory cell.

Abstract: A magnetic random access memory array includes a data storage layer having an easy axis. A non-linear first conductor is positioned on a first side of the data storage layer, wherein a portion of the first conductor has an angle of orientation that is perpendicular to the easy axis. A non-linear second conductor is positioned on a second side of the data storage layer, wherein a portion of the second conductor also has an angle of orientation that is perpendicular to the easy axis.

Abstract: Systems and methods for reducing the effect of noise while reading data from memory, are provided. One system embodiment includes a memory cell that stores a first data; multiple sensing devices that receive the first data and provide a first set of outputs; and a voting system that evaluates the first set of outputs to determine whether one of the outputs of the first set is valid data from the memory cell. One method embodiment includes reading data in parallel that is stored in a memory cell to provide outputs; and evaluating the outputs to determine whether one of the outputs is valid data from the memory cell.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. A linear error correction block code such as a Reed-Solomon code forms codewords having a plurality of symbols. In almost all cases, a corrected codeword is formed by error correction decoding a read codeword in a standard first decoder arranged to reliably identify and correct up to a predetermined number of failed symbols, or else determine an unrecoverable error. Error correction decoding of the read codeword is then attempted in a stronger second decoder, ideally being a maximum likelihood decoder arranged to form one or more closest corrected codewords.

Abstract: A multi-layer random access memory device uses a shared conductive trace for writing to the MRAM memory cells. The MRAM has N (where N is greater than 1) stacked magnetic storage elements, where each of the N magnetic storage elements is operatively positioned between a different adjacent pair of N+1 stacked conductive traces. In one embodiment, the MRAM device includes a first conductive trace for generating a first magnetic field in response to a current applied to the first conductive trace, a second conductive trace for generating a second magnetic field in response to a current applied to the second conductive trace, and a third conductive trace for generating a third magnetic field in response to a current applied to the third conductive trace.

Abstract: A magnetoresistive solid-state storage device (MRAM) employs error correction coding (ECC) to form ECC encoded stored data. In a read operation, parametric values are obtained from storage cells 16 of the device and compared to ranges to establish logical bit values, together with erasure information. The erasure information identifies symbols 206 in a block of ECC encoded data 204 which, from the parametric evaluation, are suspected to be affected by physical failures of the storage cells 16. Where the position of suspected failed symbols 206 is known from this erasure information, the ability of a decoder 22 to perform ECC decoding is substantially enhanced.

Abstract: A redundancy implementation circuit has a set of memory cells each storing an address bit of an address identifying a redundant memory location and a set of comparator circuits each connected to compare the address bit stored in a memory cell with an incoming address bit. A switch selectively connects the output of the memory cell to a redundant address line supplying the incoming address bit during a test mode. A redundant address line driver is activated for supplying an incoming address bit onto the redundant address line in a normal mode, and a test line output driver is connected to the redundant address line in a test mode for utilising the redundant address line to supply test signals onto a test path.

Abstract: A current generator provides a substantially constant current. The current generator is based on a bandgap circuit and additionally include a current setting device which is located to receive the output signal of the operational amplifier of the bandgap circuit and which is arranged to provide a substantially constant reference current. The circuit is used to particular advantage in a flash memory device.

Abstract: A memory comprises first and second arrays of memory cells organised in rows and column. The cells in each row are connected to respective wordlines and the cells in each column are connected to a respective bit line. Wordlines of the first array are addressable independently of the wordlines of the second array. A sense amplifier is provided to sense the differential between a signal on the bit line of a selected cell in one array and a reference signal. A current souce is selectively connectable to supply the reference signal for comparison with the signal on the bit line of the addressed array. The present invention allows capacitive balancing to be achieved without the need for dummy cells.

Abstract: A reference circuit is provided which generates a reference voltage which is always at least as high as a stable reference value. This is done by generating a lock signal which is maintained at a first logic level during start-up of the reference circuit and then attains a second logic level when the reference value has stabilized. The reference circuit can be a bandgap reference circuit.