Abstract: A gain circuit includes an analog section with variable gain and a digital section with variable gain. The gain steps for the digital section have a higher resolution than the gain steps for the analog section. In some implementations, gain steps can be achieved much finer than 0.1 db or less without sensitivity to device tolerances.

Abstract: An analog equalization filter is disclosed which permits higher speed and linearity than existing designs, allowing for filtering operation to the hundreds of gigahertz range. Possible applications include fixed and adaptive equalization filtering and radio frequency filtering. The filter can be entirely implemented on an integrated circuit chip. The filter is based on transmission line based delay elements and transconductance amplifiers.

Abstract: Circuits and methods for a differential circuit involve having one of more pairs of differential transistors with back-gate terminals, where each of the back-gate terminals is biased by a tunable back-gate voltage to compensate for circuit mismatches in the differential circuit and reduce or eliminate even-order harmonics in the output signal. A compensation circuit can be configured to receive data relating to the differential output signal of the differential circuit, and to supply one or more back-gate voltages to the back-gate terminals of the differential transistors to adjust threshold voltages of the differential transistors and suppress even-order harmonics in the differential output signal of the differential circuit.

Abstract: Particular embodiments of mixer designs permit greater integration on standard chips with an improvement in power and linearity to enable low-power, high-performance reception. Some embodiments feature a method of frequency conversion using at least two stages of switches to mix an input signal with reference signals. The method involves mixing a differential input signal with a first differential reference signal through a first stage of switches, generating from the first stage of switches a first frequency converted differential signal, and mixing the first frequency converted differential signal with a second differential reference signal through a second stage of switches. The method includes generating from the second stage of switches a second frequency converted differential signal. The first differential reference signal can be phase shifted from the second differential reference signal and can have a different frequency.

Abstract: Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier.

Abstract: An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.

Abstract: Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.

Abstract: Embodiments feature techniques and systems for analog and digital tuning of crystal oscillators. In one aspect, some implementations feature a method for tuning a frequency of a crystal oscillator that can include adjusting the tuning frequency of the crystal oscillator from a nominal frequency via a switched-capacitor frequency tuning circuit, the switched-capacitor frequency tuning circuit can have switchable sections to adjust the tuning of the crystal oscillator. The method can include controlling an analog control input that is coupled to a varactor within each of the switchable sections, where each of the switchable sections can include a fixed capacitor in series with the varactor and a switch. The method can involve controlling a digital control input, where the digital control input can electrically connect or disconnect one or more of the switchable sections from the crystal. There can be independent control between the digital and analog tuning mechanisms.

Abstract: Embodiments feature techniques and systems for digitally tuning a crystal oscillator circuit. In one aspect, embodiments feature a method for making a digitally tuned crystal oscillator circuit. The method involves receiving a multi-bit input signal into a digital modulator, modulating the multi-bit input signal with the digital modulator by oversampling or by noiseshaping and oversampling to produce a digitally-modulated output signal having a lower number of bits than the multi-bit input signal. The method also involves coupling a tuning capacitor with the crystal oscillator circuit, and coupling the digitally-modulated output signal from the digital modulator to the crystal oscillator circuit and the tuning capacitor. In some embodiments, the digital modulator can a delta-sigma modulator, a noiseshaping modulator, a delta modulator, a pulse width modulator, a differential modulator, or a continuous-slope delta modulator.

Abstract: A high-speed latch is disclosed that can function at high-speed input clocking frequencies. The active loads used within the latch design exhibit an input impedance that is inductive to the rest of the circuit to improve the driving capability of the overall latch in the presence of loading capacitances. The latch circuit, when used in a system or stand alone divider, will consume very low power while reducing the silicon die area. Possible applications include but are not limited to frequency dividing and counting applications. Of particular interest is the use of this high-speed latch in a prescaler divider as a part of a charge pump phase-locked loop design for single chip CMOS multi-band and multi-standard radio frequency transceiver integrated circuits.

Abstract: Circuits and methods for a mixer circuit involve having a first transistor with first and second terminals, where the first terminal is configured to handle an input RF signal. The mixer has a second transistor including a first terminal coupled to the second terminal of the first transistor, a second terminal configured to handle an input oscillator signal, and a third terminal configured to output an intermediate frequency (IF) signal. The IF signal includes a mixed product of the input RF signal and the input oscillator signal. A gate oxide thickness of the first transistor is less than a gate oxide thickness of the second transistor to provide enhanced linearity and a low noise figure. One or more of the mixers can be implemented in a receiver design.

Abstract: Sharing one or more load inductors comprises receiving a first input signal at a first terminal of a first amplifier and amplifying the first input signal using the first amplifier. The first amplifier is coupled to one or more load inductors at a second terminal of the first amplifier and is coupled to one or more dedicated source inductors at a third terminal of the first amplifier. Also, a second input signal is received at a first terminal of a second amplifier amplifying the second input signal using the second amplifier. The second amplifier is coupled to the one or more load inductors at a second terminal of the second amplifier and is coupled to one or more dedicated source inductors at a third terminal of the second amplifier.

Abstract: In some implementations, a system includes a low-power voltage regulator that can switch between three power modes: a power shutdown mode, a low power mode, and a higher power mode. The system includes a selector coupled to the voltage regulator to switch between the low power mode and the higher power mode, and a switch to switch between the power shutdown mode and the low or higher power mode. The system also has a control circuit to control the switch and the selector to control operation of the voltage regulator in any of the three power modes. A total current used in the voltage regulator in the low power mode is on the order of microamps or nanoamps. The voltage regulator in the low power mode has two to more orders of magnitude of lower current use than the voltage regulator in the higher power mode.

Abstract: Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.

Abstract: An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.

Abstract: Generally, implementations provide a circuit framework that uses phase and amplitude modulation with several voltage-controlled-oscillators (VCOs) and corresponding variable gain amplifiers (VGAs) to generate and amplitude and phase modulated signals that are summed to an output signal for a transmitter circuit. The implementations can involve decomposing an input signal into a number of decomposed signals using a signal decomposer component, in which each of decomposed signals includes phase and amplitude information. The signal decomposer component can interact with each of the VCOs and corresponding VGAs to conduct the phase and amplitude modulation for the amplitude and phase modulated signals. The multiple standard transmitter circuit can be used for one or more communication standards, such as Global System for Mobile Communications (GSM), a Wideband Code Division Multiple Access (WCDMA), or High-Speed Uplink Packet Access (HSUPA), among others.

Abstract: A radio frequency receiver includes a passive mixer configured to receive and RF signal and a low input impedance circuit configured to receive the output of the passive mixer.

Abstract: Techniques and systems for receiving a signal at a first component with an adjustable gain, and adjusting the gain of the first component to a first gain value using a first gain step. Amplifying the signal with the first gain value, generating a first amplified signal, and receiving the first amplified signal at a second component with an adjustable gain. Adjusting a gain of the second component to a second gain value using a second gain step. The net gain step is smaller than one of the first or second gain step. Amplifying the first amplified signal with the second gain value to generate a second amplified signal, and receiving the second amplified signal at a filtering component. A transient response introduced by the filtering component on the second amplified signal is smaller than the transient response that would be introduced by the filtering component on the first amplified signal.

Abstract: A gain circuit includes an analog section with variable gain and a digital section with variable gain. The gain steps for the digital section have a higher resolution than the gain steps for the analog section. In some implementations, gain steps can be achieved much finer than 0.1 db or less without sensitivity to device tolerances.

Abstract: Embodiments feature techniques and systems for analog and digital tuning of crystal oscillators. In one aspect, some implementations feature a method for tuning a frequency of a crystal oscillator that can include adjusting the tuning frequency of the crystal oscillator from a nominal frequency via a switched-capacitor frequency tuning circuit, the switched-capacitor frequency tuning circuit can have switchable sections to adjust the tuning of the crystal oscillator. The method can include controlling an analog control input that is coupled to a varactor within each of the switchable sections, where each of the switchable sections can include a fixed capacitor in series with the varactor and a switch. The method can involve controlling a digital control input, where the digital control input can electrically connect or disconnect one or more of the switchable sections from the crystal. There can be independent control between the digital and analog tuning mechanisms.