Abstract: A valve apparatus for controlling fluid flow between a fluid passage and a fluid delivery conduit therein includes a valve housing having first and second housing ports spaced therealong, and a driven member driveable toward and away from the first housing port. A closure member having a port is coupled to the driven member and slidable therealong. The driven member and closure member close and open the closure member port during movement of the driven member toward and away from the first port to induce and relieve a pressure differential, exerted on the closure member by fluid entering the housing, acting to slide the closure member along the driven member to close the first housing port. An inductive coil extends about an open end of the housing to receive a coil-equipped end of a probe therein to communicate the probe with monitoring and control systems across the valve.

Abstract: A valve apparatus for controlling fluid flow between a fluid passage and a fluid delivery conduit therein includes a valve housing having first and second housing ports spaced therealong, and a driven member driveable toward and away from the first housing port. A closure member having a port is coupled to the driven member and slidable therealong. The driven member and closure member close and open the closure member port during movement of the driven member toward and away from the first port to induce and relieve a pressure differential, exerted on the closure member by fluid entering the housing, acting to slide the closure member along the driven member to close the first housing port. An inductive coil extends about an open end of the housing to receive a coil-equipped end of a probe therein to communicate the probe with monitoring and control systems across the valve.

Abstract: A valve apparatus for controlling fluid flow between a fluid passage and a fluid delivery conduit therein includes a valve housing having first and second housing ports spaced therealong, and a driven member driveable toward and away from the first housing port. A closure member having a port is coupled to the driven member and slidable therealong. The driven member and closure member close and open the closure member port during movement of the driven member toward and away from the first port to induce and relieve a pressure differential, exerted on the closure member by fluid entering the housing, acting to slide the closure member along the driven member to close the first housing port. An inductive coil extends about an open end of the housing to receive a coil-equipped end of a probe therein to communicate the probe with monitoring and control systems across the valve.

Abstract: A phase and edge aligned local clock signal is generated in a data-receiving unit by deriving the local clock signal from a forwarded clock signal received from a transmitting unit. The local clock signal is a delayed replica of the forwarded clock signal, such that the receiving unit maintains synchronism between the local clock signal and the forwarded clock signal. Thus, transfers from an input latch to other components in the receiving unit can be effected in step with the receipt of data in the input latch.

Abstract: A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates signals in response to receiving clock signals from a clock source. A second timer detects the presence or absence of signals from the first timer and in response to an absence outputs a circuit reset signal to a circuit. The circuit in turn issues a reset signal to the PLL and to other systems.

Abstract: A computer system comprising a memory system that comprises a plurality of memory modules; and a memory controller that accesses the plurality of memory modules to service memory requests. The computer system also comprises an error-type memory controller that configures the noted access such that the memory controller can continue to access a failed one of the plurality of memory modules that incurred a soft error.

Abstract: A phase-locked loop (PLL) circuit is used to synchronize data transfers between a fast clock and a slow clock domain. The data transfer can be deterministic, where the fast clocks are generated by a first PLL and the slow clocks are generated by a second PLL. The second PLL is used to create a phase relationship between the first PLL output clock and a third PLL output clock. The phase relationship can provide for a deterministic data transfer.

Abstract: A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates signals in response to receiving clock signals from a clock source. A second timer detects the presence or absence of signals from the first timer and in response to an absence outputs a circuit reset signal to a circuit.

Abstract: An automated backplane cable connection system (and method) for manually connecting a cluster of processor modules to other modules or I/O boxes uses a programmed server management control console which identifies connection terminals provided on the processors/I/O boxes and controls LEDs which are associated with the connection terminals, on a one to one basis. The programmed server management console uses diagnostic circuitry and causes LEDs corresponding to connection terminals engaged by a newly made cable connection to initially light up, and enables them to turn off if the newly made cable connection is proper as verified by the diagnostic circuitry. The cluster of processor modules may be connected to a plurality of I/O boxes through an Ethernet LAN. The processor modules or I/O boxes may have sufficient nonvolatile memory to remember backplane cable connections which have already been made according to user needs, as initially guided by the programmed server management control console.

Abstract: An initialization/reset circuit automatically resets and initializes a clocking subsystem having a phase locked loop (PLL) within a data processing system. The logic circuit is contained within an input/output (I/O) interface of the system. Clock signals are provided from a clock source of the data processing system to the PLL. In addition to the PLL, the initialization/reset logic circuit comprises a counter, a first timer circuit and a second watchdog timer.

Abstract: In accordance with the present invention, an apparatus includes a system bus having memory bank available signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank. Each memory module includes a mechanism for associating each memory bank with one of the memory bank available signals. Further, each memory module includes logic for determining an availability status of each memory bank and for providing the associated memory bank busy signal with values reflecting the availability status of the memory bank. Additionally, at least two commander modules are coupled to the system bus and include logic, responsive to the memory bank available signals for preventing the commander module from gaining control of the system bus when the commander is attempting to access a memory bank determined to be unavailable. With such an arrangement, only commander modules seeking to access memory banks which are available will be allowed to gain control of the system bus.

Abstract: A pair of tracks extend between the side frame rails of a minivan, each track having an upper horizontal side, a lower horizontal side, and a vertical side. A powered trolley has a first set of wheels located between the horizontal sides of each track and a second set of wheels engaging the vertical sides of the tracks. A ramp or platform has an inner end coupled to the trolley and an outer end riding on the upper horizontal side of the track. At the outer end of each track, the upper horizontal side angles upwardly away from horizontal, causing the outer end of the ramp to lower when extended.

Abstract: A transmitting node generates error correction symbols by encoding data using error correction code integrated with information which identifies the data cycle in which the data are to be transmitted, the integrated encoded data having the same number of bits as the error correction code has alone. A node receiving the data generates error correction symbols encoding the received data using error correction code integrated with information which identifies the data cycle in which the receiving node is operating. A comparison is made of the transmitting node error correction symbols received with the receiving node generated error correction symbols, and if the two sets of symbols do not match, the receiving node detects and, if possible, corrects errors in the data using the error correction code. Alternatively, the receiving node may remove the data cycle information from the received error correction symbols and perform a comparison using standard error correction code applied to the received data.

Abstract: In a data processing system having a plurality of commander nodes and at least one resource node interconnected by a system bus, a bus arbitration technique determines which commander node is to gain control of the system bus to access the resource node. The bus arbitration technique assigns priority levels to all commander nodes, with at least one commander node receiving more than one priority level. Each priority level has an associated signal path. During each arbitration, each contending commander node can activate or assert the signal path associated with its priority level, and the commander node having more than one priority level can assert the signal path associated with any one of its priority levels. All commander nodes monitor all the signal paths to determine the identity of the contending commander node that asserted the signal path associated with the highest priority level among those that were asserted, and, thus, the contending commander node that "won" the arbitration.

Abstract: Construction for a water bed including a bladder filled with water or other fluid, a foam rubber framing element which is provided with a bladder receiving recess which provides a peripheral frame for the bladder and an upper surface within the frame upon which the bladder will rest. The foam rubber framing unit and the water bladder is supported and carried by a mattress and box spring of normal construction or may be supported and carried by the box spring singularly.