Abstract: A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

Abstract: Systems and methods are provided for analyzing the timing of circuits, including integrated circuits, by taking into account the location of cells or elements in the paths or logic cones of the circuit. In one embodiment, a bounding region may be defined around cells or elements of interest, and the size of the bounding region may be used to calculate a timing slack variation factor. The size of the bounding region may be adjusted to account for variability in timing delays. In other embodiments, centroids may be calculated using either the location or the delay-weighted location of elements or cells within the path or cone and the centroids used to calculate timing slack variation factor. The timing slack variation factors are used to calculate a new timing slack for the path or logic cone of the circuit.

Abstract: The invention provides a device having two components: a needle advancing apparatus slidable longitudinally along a catheter to advance needles into a tissue membrane, such as a blood vessel wall, around an opening in the membrane; and, a suture retrieval assembly insertable through the catheter beyond a distal side of the tissue membrane. The needle advancing apparatus advances suture through the tissue wall. The suture retrieval assembly grabs the suture on the distal side of the tissue membrane for extraction thereof through the opening in the tissue membrane. A method for suturing a membrane beneath the patient's skin is also disclosed.

Abstract: The present invention relates to methods of treating polycystic ovary syndrome (PCOS) comprising administering glucagon-like peptide-1 (GLP-1), exendin, and analogs and agonists thereof, to subjects suffering therefrom.

Abstract: A method for reticle design correction and electrical parameter extraction of a multi-cell reticle design. The method including: selecting a subset of cell designs of a multi-cell reticle design, each cell design of the subset of cell designs having a corresponding shape to process, for each cell design of the subset of cell designs determining a respective cell design location of the corresponding shape; determining a common shapes processing rule for all corresponding shapes of each cell design based on the respective cell design locations of each of the corresponding shapes; and performing shapes processing of the corresponding shape only of a single cell design of the subset of cell designs to generate resulting data for the subset of cell designs. Also a computer usable medium including computer readable program code having an algorithm adapted to implement the method for reticle design correction and electrical extraction.

Abstract: A method and device for determining a delay of a gate driven by a driving gate with different ground or supply voltages. The method includes determining from the supply and ground voltages for the driven gate and its driving gate an adjusted supply voltage value, and applying the adjusted supply voltage value as a single voltage parameter to a pre-characterized delay model for the driven gate. The device is structured to perform the method.

Abstract: Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.

Abstract: The invention provides a device having two components: a needle advancing apparatus slidable longitudinally along a catheter to advance needles into a tissue membrane, such as a blood vessel wall, around an opening in the membrane; and, a suture retrieval assembly insertable through the catheter beyond a distal side of the tissue membrane. The needle advancing apparatus advances suture through the tissue wall. The suture retrieval assembly grabs the suture on the distal side of the tissue membrane for extraction thereof through the opening in the tissue membrane. A method for suturing a membrane beneath the patient's skin is also disclosed.

Abstract: A method in accordance with the invention for modeling period jitter for testing a modeled logic circuit. Clock signals can be derived from a phase lock loop having a voltage controlled oscillator for use to evaluate timing problems within a modeled circuit. An estimation of period jitter for the modeled clock signals can be made by considering the number of periods of the voltage controlled oscillator signal which generates the clock signal occurring within a test interval. By using the relationship as an index to a table, a value of period jitter may be obtained from a table which increases longer the timing interval being considered. Instructions for carrying out the steps of correcting intervals between clock signals used in static timing tests may be stored on a computer readable medium along with a table containing the amount of period jitter as a function of the number of VCO periods occurring within a testing period.

Abstract: A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a first wiring path, a second wiring path, etc. Two or more of the wiring paths are designed to have matching timing, such that the time needed for a signal to travel along the first wiring path is about the same time needed for a signal to travel along the second wiring path, the third path, etc. The method/service designs one or all of the wiring paths to make the paths traverse wire segments of about the same length and orientation, within each wiring level that the first wiring path and the second wiring path traverse. Also, this process makes the first wiring path and the second wiring path traverse the wire segments in the same order, within each wiring level that the first wiring path and the second wiring path traverse.

Abstract: A method of, and a system for, determining an extreme value of a voltage dependent parameter of an integrated circuit design is provided. The method includes determining a plurality of current waveforms, each of the plurality of waveforms corresponding to one of a plurality of aggressor objects in the design of the integrated circuit; applying each of the plurality of current waveforms to a subset of the plurality of power bus nodes, the subset of the plurality of power bus nodes being designed to supply power to a corresponding one of the plurality of aggressor objects; determining a plurality of voltage waveforms, each of the plurality of voltage waveforms being at one of the plurality of power bus nodes and corresponding to one of the plurality of current waveforms; using the plurality of voltage waveforms to determine the extreme value.

Abstract: A hybrid linear wire model for tuning the transistor widths of circuits linked by RC interconnects is described. The method uses two embedded simulators during the tuning process on netlists that contain resistors (Rs). A Timing oriented simulator is used only for timing purposes on the original netlist that includes all the Rs. A Gradient oriented simulator is then run only on the modified netlist with all Rs shorted and within the iterative loop of the tuner to compute gradients. The present hybrid method achieves a significant improvement in computational speed. The Timing oriented simulator is fast and accurate for only timing netlists with Rs, but cannot compute gradients efficiently. The Gradient oriented simulator computes gradients efficiently but cannot do so in the presence of Rs.

Abstract: Methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis (STA). The methods involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths. An adjusted timing slack is calculated using the delay contributions of elements having dissimilar delays. In some embodiments, the delay contributions of elements having dissimilar delays are root sum squared. Embodiments of the invention provide methods for reducing the pessimism due to both cell-based and wire-dependent delays. The delays considered in embodiments of the invention may include delays due to the location of elements in a path.

Abstract: A method, system and program product are described for generating a clock distribution network on an integrated circuit by determining an allowable placement region for each of a set of clock tree leaf elements in the integrated circuit. This allowable placement region is generated by determining and intersecting a set of sub-regions under different constraints, each of which identifies an area in which the clock tree leaf element is placed to satisfy the respective constraint. Constraints for which sub-regions are determined include timing constraints in the form of slacks and congestion constraints. After allowable placement regions have been determined, the clock tree leaf elements are clustered, and each clock tree leaf element is placed at a location within its allowable placement region which minimizes some cost function for that clustering.

Abstract: Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

Abstract: The invention provides a device having two components: a needle advancing apparatus slidable longitudinally along a catheter to advance needles into a tissue membrane, such as a blood vessel wall, around an opening in the membrane; and, a suture retrieval assembly insertable through the catheter beyond a distal side of the tissue membrane. The needle advancing apparatus advances suture through the tissue wall. The suture retrieval assembly grabs the suture on the distal side of the tissue membrane for extraction thereof through the opening in the tissue membrane. A method for suturing a membrane beneath the patient's skin is also disclosed.

Abstract: A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis is performed on each parameter by noting the difference in timing, typically on endpoint slacks, when the parameter is varied. This step is repeated for every independent parameter. A failure coefficient is then calculated from the reference slack and the sensitivity of slack for each of the timing endpoints and a determination is made as to whether at least one timing endpoint fails a threshold test. Failing timing endpoints are then prioritized for modification according to their failure coefficients. The total number of runs required is one run that is used as a reference run, plus one additional run for each parameter.

Abstract: A method for and an apparatus in which the FSOURCE connection in a fuse domain is split into multiple nets, allowing flexible placement of primary fuses in the floorplan, is provided. In particular, multiple FSOURCE connections (e.g. C4 pads or wire pads) are provided in the floorplan, allowing flexible placement of primary fuses without additional overhead.

Abstract: A differential sinusoidal signal pair is generated on an integrated circuit (IC). The differential sinusoidal signal pair is distributed to clock receiver circuits, which may be differential amplifiers. The clock receiver circuits receive the differential sinusoidal signal pair and convert the differential sinusoidal pair to local clock signals. Power consumption and noise generation are reduced as compared to conventional clock signal distribution arrangements.

Abstract: The present invention relates to methods of treating intermittent claudication comprising administering glucagon-like peptide-1 (GLP-1) molecules to subjects suffering therefrom.