Abstract: A system and method of error detection for unordered data delivery. A data set is received, the data set including a plurality of data segments, each having a descriptor; a data packet for each of the plurality of data segments, each of the data packets including the data segment and the descriptor for each of the plurality of data segments; and a source cyclic redundancy check (CRC) code for each of the data packets. The source CRC codes are stored as a source CRC table and a received CRC code is computed for a first data packet. It is determined whether the received CRC code for the first data packet is in the source CRC table and the first data packet is used when the received CRC code for the first data packet is in the source CRC table.

Abstract: Prefetching data and instructions from a hierarchical memory based upon trajectories and patterns of prior memory fetches. Portions of the data are stored in a slower main memory and are transferred to faster intermediate memory between a requester and the slower main memory. The selected data items are retrieved from the slower main memory into a prefetch read buffer as an intermediate memory prior to any request from the requester for the particular selected and prefetched data. The address and size of the prefetched data is derived from the history, pattern, or trajectory of prior memory reads.

Abstract: An apparatus for regulating power allocated to components within a computer system includes a sensor to sense power drawn by a first device within a computer system, the first device having device resources needed to satisfy functional demand required of the first device. A second sensor is provided to sense power drawn by a second device within the computer system, the second device having device resources needed to satisfy functional demand required of the second device. A power-monitoring module is provided to monitor the power drawn and the functional demand required of the first and second devices. A system control module, operably connected to the power-monitoring modules, is provided to regulate power allocated to the first and second devices by optimizing use of the device resources in accordance with the temperature, power drawn, and respective functional demands of the devices.

Abstract: A hardware based solution to CPU utilization and power management that avoids an additional set of software tasks to monitor CPU utilization. The system has a CPU, a counter; a monitor, and a clock. The clock provides a CLK signal to the counter when a software task is running on the CPU, and the counter counts the number of clock pulses since a RESET. The monitor samples and holds the value of the counter at the last RESET. The counter outputs a signal to the monitor that is responsive to the count content at the time of the last reset. The monitor outputs this value as a control signal. This control signal may be a power control signal, a function control signal, or even a clock control signal, responsive to count content. For example, the counter may output a control signal reducing power input or clock pulse input to the CPU responsive to monitor value when the CPU utilization is below a threshold.

Abstract: A method, system, and computer program for predicting the failure of an electronic circuit. One embodiment of the invention monitors the current utilization, environment conditions, and operating conditions of the electronic circuit. A system manager is altered if the current utilization of the electronic circuit is outside a pass range at the measured environmental conditions and the measured operating conditions of the electronic circuit. The invention may also be configured such that if the electronic circuit fails, the electronic circuit is isolated from among a plurality of potentially failed electronic circuits using the measured current utilization, environment conditions, and operating conditions of the electronic circuit.