Abstract: Various embodiments provide a direct current (DC)-DC converter circuit. The DC-DC converter circuit includes a control circuit to switch the DC-DC converter circuit between a charge state, a discharge state, and a tri-state mode. As part of a first control loop, the control circuit may switch the DC-DC converter between the charge state and the discharge state based on the output voltage to provide the output voltage with the target voltage level. Additionally, as part of a second control loop, the control circuit may switch the DC-DC converter between the charge state and the discharge state based on the current through an inductor of the DC-DC converter. The second control loop may provide overcurrent protection for the DC-DC converter. Other embodiments may be described and claimed.

Abstract: Systems, methods, and circuitries for regulating voltage supplied to a power amplifier are disclosed. In one example, a buck-boost control system is configured to control a buck-boost converter to operate in either a buck mode or a boost mode. The system includes compensator circuitry configured to determine a target current based on a difference between a target voltage and a regulated output voltage of the buck-boost converter and determine a tolerance current that, with the target current, defines a range of expected coil current for the present operating mode. Based on the difference between the target voltage and the regulated output voltage, a charge control signal or a discharge control signal is generated for the converter to cause the coil current to approach the target current. Mode control circuitry is configured to switch the buck-boost converter to the other operating mode when the coil current reaches the tolerance current.

Abstract: Various embodiments provide a direct current (DC)-DC converter circuit. The DC-DC converter circuit includes a control circuit to switch the DC-DC converter circuit between a charge state, a discharge state, and a tri-state mode. As part of a first control loop, the control circuit may switch the DC-DC converter between the charge state and the discharge state based on the output voltage to provide the output voltage with the target voltage level. Additionally, as part of a second control loop, the control circuit may switch the DC-DC converter between the charge state and the discharge state based on the current through an inductor of the DC-DC converter. The second control loop may provide overcurrent protection for the DC-DC converter. Other embodiments may be described and claimed.

Abstract: Described is an apparatus which comprises: a plurality of bridges which are operable to drive respective signals for one or more power supply rails; a plurality of controllers; and a main controller to couple one or more controllers from the plurality of controllers to one or more bridges from the plurality of bridges.

Abstract: A digitally controlled buck boost regulator includes an H-bridge circuit including a plurality of switches configured to receive an input voltage signal and generate an output voltage signal based on the input voltage signal and switching signals provided thereto. A controller generates a pulse width modulation (PWM) control value in response to a value of the output voltage signal, and a quantizer/mapper receives the PWM control value and provides a first mapping to a mapped PWM control value if the PWM control value is outside a predetermined range of PWM control values, and generates a second mapping to a mapped PWM control value if the PWM control value is within the predetermined range. A digital pulse width modulator is configured to generate switching signals based on the mapped PWM control value, and provide the generated switching signals to the H-bridge circuit.

Abstract: Described is an apparatus which comprises: a plurality of bridges which are operable to drive respective signals for one or more power supply rails; a plurality of controllers; and a main controller to couple one or more controllers from the plurality of controllers to one or more bridges from the plurality of bridges.

Abstract: A digitally controlled buck boost regulator includes an H-bridge circuit including a plurality of switches configured to receive an input voltage signal and generate an output voltage signal based on the input voltage signal and switching signals provided thereto. A controller generates a pulse width modulation (PWM) control value in response to a value of the output voltage signal, and a quantizer/mapper receives the PWM control value and provides a first mapping to a mapped PWM control value if the PWM control value is outside a predetermined range of PWM control values, and generates a second mapping to a mapped PWM control value if the PWM control value is within the predetermined range. A digital pulse width modulator is configured to generate switching signals based on the mapped PWM control value, and provide the generated switching signals to the H-bridge circuit.

Abstract: In an embodiment, a circuit is disclosed comprising a circuit portion coupled to a terminal and a calibration circuit portion coupled to said terminal.

Abstract: An integrated circuit includes an output terminal to be coupled to a light-emitting diode, an output circuit coupled to the output terminal, the output circuit being configured to supply an operating signal to the light-emitting diode, a measuring circuit coupled to the output terminal and a control circuit coupled to the measuring circuit. The measuring circuit is configured to sense on the output terminal a signal value outside an operating regime of the light-emitting diode, the signal value being a voltage below a forward voltage of the light-emitting diode or a current below a threshold current of the light-emitting diode. The control circuit is configured to configure at least one function of the integrated circuit when the signal value as sensed by the measuring circuit corresponds to a voltage below the forward voltage of the light-emitting diode or a current below the threshold current of the light-emitting diode.

Abstract: In an embodiment, a circuit is disclosed comprising a circuit portion coupled to a terminal and a calibration circuit portion coupled to said terminal.

Abstract: An integrated circuit comprises an output terminal to be coupled to a non-linear circuit element, an output circuit coupled to the output terminal, the output circuit being configured to supply an operating signal to the non-linear circuit element, a measuring circuit coupled to the output terminal, the measuring circuit being configured to sense on the output terminal a signal value outside an operating regime of the non-linear circuit element, and a control circuit coupled to the measuring circuit, the control circuit being configured to configure at least one function of the integrated circuit on the basis of the signal value sensed by the measuring circuit.

Abstract: A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a communications path by a section controller. The section controller determines the addresses in the memory devices storing the requested data, transfers these addresses to those memory devices storing the requested data, and transfers an identifier to the memory interface device. The memory device, in response, reads the data and transfers the data to its corresponding memory interface device. The memory interface device then adds to the data the identifier it received from the section controller and forwards the requested bits towards their destination, such that the data need not pass through the section controller.

Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.

Abstract: A storage system that may include one or more memory sections, one or more switches, and a management system. The memory sections include memory devices and a section controller capable of detecting faults with the memory section and transmitting messages to the management system regarding detected faults. The storage system may include a management system capable of receiving fault messages from the section controllers and removing from service the faulty memory sections. Additionally, the management system may determine routing algorithms for the one or more switches.

Abstract: A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers and then serially shifted through the shift registers until it is output from the sets of shift registers and transferred to its destination. Additionally, the data may be read from and loaded into the memory devices to/from the sets of shift registers such that the shifting of the shift registers is uninterrupted during the reading and/or loading of data. Additionally, data from the memory devices may be loaded into two or more parallel chains of shift registers and then serially shifted through the shift register chains.