Abstract: A semiconductor device architecture includes a silicon substrate having sidewalls that are passivated by encapsulating the sidewalls in dielectric materials having high electric field strength. Encapsulating all the sidewalls using high field strength dielectric materials eliminates electrical paths in air or vacuum and confines the electric fields in these high field strength materials, increasing the breakdown voltage relative to unencapsulated devices and allowing the device to withstand greater standoff voltages. In some cases, encapsulating the sidewalls in this manner can allow the device to withstand voltages of 500V or greater.

Abstract: A semiconductor device architecture includes a silicon substrate having sidewalls that are passivated by encapsulating the sidewalls in dielectric materials having high electric field strength. Encapsulating all the sidewalls using high field strength dielectric materials eliminates electrical paths in air or vacuum and confines the electric fields in these high field strength materials, increasing the breakdown voltage relative to unencapsulated devices and allowing the device to withstand greater standoff voltages. In some cases, encapsulating the sidewalls in this manner can allow the device to withstand voltages of 500V or greater.

Abstract: Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes.

Abstract: A semiconductor device architecture includes a silicon substrate having sidewalls that are passivated by encapsulating the sidewalls in dielectric materials having high electric field strength. Encapsulating all the sidewalls using high field strength dielectric materials eliminates electrical paths in air or vacuum and confines the electric fields in these high field strength materials, increasing the breakdown voltage relative to unencapsulated devices and allowing the device to withstand greater standoff voltages. In some cases, encapsulating the sidewalls in this manner can allow the device to withstand voltages of 500V or greater.

Abstract: Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes.

Abstract: Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes.

Abstract: Systems and methods are provided for efficiently permitting the transmission and receipt of trading messages between message sources configured to use a variety of different protocols. Messaging gateways may be configured to reformat messages for proper transmission across a transport mechanism. Messaging gateways may also insert sequence and group information into message headers to facilitate processing messages in the proper order. Messages may be processed with processing threads that are dynamically allocated by messaging gateways.

Abstract: Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes.

Abstract: Systems and methods are provided for efficiently permitting the transmission and receipt of trading messages between message sources configured to use a variety of different protocols. Messaging gateways may be configured to reformat messages for proper transmission across a transport mechanism. Routers may be dynamically partitioned so that manual reconfiguration is not required when sources and/or routers are added or deleted. The routers may be configured to route messages based on content to limit the amount of formatting required at message sources.

Abstract: Systems and methods are provided for efficiently permitting the transmission and receipt of trading messages between message sources configured to use a variety of different protocols. Messaging gateways may be configured to reformat messages for proper transmission across a transport mechanism. Routers may be dynamically partitioned so that manual reconfiguration is not required when sources and/or routers are added or deleted. The routers may be configured to route messages based on content to limit the amount of formatting required at message sources.

Abstract: A method and apparatus are disclosed for reducing crosstalk and dispersion in a crosspoint monolithic microwave integrated circuit (MMIC) switch array operating in a range between DC and microwave frequencies. In accordance with an exemplary embodiment, the crosspoint MMIC switch array includes a dielectric stack, a substrate, a first ground plane, a plurality of thyristor switches, a plurality of signal transmission lines arranged in rows; and a plurality of signal transmission lines arranged in columns. The plurality of signal transmission lines arranged in columns intersect the plurality of signal transmission lines arranged in rows at a plurality of intersection points. Each of the plurality of thyristor switches is associated with one of the plurality of intersection points. Each of the plurality of thyristor switches is in electrical contact with the signal transmission lines that intersect at the associated intersection point.

Abstract: A heterojunction P—I—N diode switch comprises a first layer of doped semiconductor material of a first doping type, a second layer of doped semiconductor material of a second doping type and a substrate on which is disposed the first and second layers. An intrinsic layer of semiconductor material is disposed between the first layer and second layer. The semiconductor material composition of at least one of the first layer and second layer is sufficiently different from that of the intrinsic layer so as to form a heterojunction therebetween, creating an energy barrier in which injected carriers from the junction are confined by the barrier, effectively reducing the series resistance within the I region of the P—I—N diode and the insertion loss relative to that of homojunction P—I—N diodes.

Abstract: A method and apparatus are disclosed for reducing crosstalk and dispersion in a crosspoint monolithic microwave integrated circuit (MMIC) switch array operating in a range between DC and microwave frequencies. In accordance with an exemplary embodiment, the crosspoint MMIC switch array includes a dielectric stack, a substrate, a first ground plane, a plurality of thyristor switches, a plurality of signal transmission lines arranged in rows; and a plurality of signal transmission lines arranged in columns. The plurality of signal transmission lines arranged in columns intersect the plurality of signal transmission lines arranged in rows at a plurality of intersection points. Each of the plurality of thyristor switches is associated with one of the plurality of intersection points. Each of the plurality of thyristor switches is in electrical contact with the signal transmission lines that intersect at the associated intersection point.