Abstract: Virtualized scan chain testing in a random access memory array, and related methods and computer-readable media are disclosed. To facilitate virtualized scan chain testing, the memory array includes an integrated test circuit that causes the memory array to behave as a serialized scan chain. The integrated test circuit forces serialized write and read access to offset entries in the memory array on each scan cycle in a scan mode based on received serialized test data. After the number of scan cycles equals the number of entries the memory array, the entries in the memory array are fully initialized with test data from the serial test data flow. In subsequent scan cycles, the integrated test circuit continues to perform serial read operations to cause stored serial test data to be serially shifted out as an output serial data flow that then be compared to the original serial test data.

Abstract: A wrecker vehicle includes a chassis, a boom coupled with the chassis, and a hoist device coupled with the chassis, the hoist device configured to engage a line to position a piece of equipment relative to the chassis. The vehicle may also include a controller configured to receive rigging setup data. The controller may further determine a first utilization state, wherein the first utilization state is a line load utilization state of the line, and a second utilization state, wherein the second utilization state is a first block load utilization state of a first sheave block. Further, the controller may be configured to determine, based on a comparison of the first utilization state to a first threshold and the second utilization state to a second threshold, a rigging setup state, and provide an indication of the rigging setup state.

Abstract: A method and system for implementing a fantasy sports team league. The fantasy sports team league provides team managers a way of competing in fantasy sports competitions that addresses the weaknesses of existing opportunities. This presented fantasy sports team league provides an unconventional season-long game-play format incorporating a salary cap and dynamic pricing model, and it provides practical applications including several new and unconventional features for fantasy team managers to experience.

Abstract: An interactive voice response (IVR) platform running a voice application for use with a voice client is extended to support text messaging clients and other clients of other media types on other channels. An application-to-text messaging interface interfaces with text messaging clients via a text messaging protocol transport and interfaces with the IVR via an API. It includes a user/application manager to handle user and application accounts and a state/session manager to handle state information required by the text messaging operations and to handle sessions maintained by the IVR. Text modules are implemented having text synthesis and text recognition with a dictionary/grammar. These allow voice-specific application scripts to be interpreted in a text channel. The extended multi-channel platform supports an open source text messaging network and also through a transport gateways to other types of text messaging clients.

Abstract: An interactive voice response (IVR) platform running a voice application for use with a voice client is extended to support text messaging clients and other clients of other media types on other channels. An application-to-text messaging interface interfaces with text messaging clients via a text messaging protocol transport and interfaces with the IVR via an API. It includes a user/application manager to handle user and application accounts and a state/session manager to handle state information required by the text messaging operations and to handle sessions maintained by the IVR. Text modules are implemented having text synthesis and text recognition with a dictionary/grammar. These allow voice-specific application scripts to be interpreted in a text channel. The extended multi-channel platform supports an open source text messaging network and also through a transport gateways to other types of text messaging clients.

Abstract: An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will be in the same state.

Abstract: An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will be in the same state.

Abstract: A control mechanism for tambour-type door closures helically wound about a winding sleeve for use in combination with cabinetry and including a worm/pinion gear combination releasably locked against free rotation, with controlled rotation of the worm facilitating adjustment of spring tension for controlled ongoing smooth operation of the tambour door closure between open and closed dispositions. The worm/pinion gear combination is coupled to a coiled spring which is helically wound about the tambour door winding spindle with one end of the coil spring being anchored to the rotatable winding spindle means, and with the other being coupled to and fixed for controlled rotational movement with the pinion component of the worm/pinion gear combination. Controlled rotatable motion of the worm is facilitated through the clutching action of the knurled end terminal of the worm gear shaft.

Abstract: A reversibly positionable shelving unit housed within a cabinet enclosure and consisting of a frame with opposed top, bottom, and intermediate supports, each with a laterally disposed support post engaging channel formed therein. An upright spine or support post is rigidly secured to and extends between the top and bottom supports, and is disposed adjacent one lateral edge surface of the supports medially between opposed front and rear edge plate surfaces, with the outer surfaces of the supports having track followers coupled thereto. Camming support means are coupled to each support, and adapted to releasably, frictionally and grippingly engage the edge of the spine to lock the shelves in cantilevered support with the spine. Matching upper and lower guide slots are formed in the enclosure for engaging the follower means, with a linear bearing secured to the lower panel and in engagement with the undersurface of the bottom-most support.

Abstract: A word line block, a data block and at least one memory cell form a memory architecture and impose no special timing requirements to handle the synchronization of the outputs of the word line block with the data block. Further, the word line block contains a transmitting transistor and the data block contains a functionally similar transmitting transistor. These transmitting transistors responsive to a write enable signal and a clock signal synchronize a selection signal supplied to the memory cell when data is also supplied to the memory cell. Furthermore, a place in route tool can automatically place and route the word line block, the data block and the at least one memory cell based on chip requirements. Also, with the clock signal proximate the output of the word line block and data block, the place and route tool is able to automatically place and route the blocks and the at least one memory cell to compensate for any calculated interconnection delays.

Abstract: A circuit for compensating for MOS device response to supply voltage variations, as well as temperature and process variations, in an integrated circuit device. The compensation circuit produces a reference voltage which modulates the gate bias voltage of a MOS transistor such that the gate-to-source bias of the MOS transistor is varied to compensate for variations in the supply voltage as well as for variations in the temperature and manufacturing process. The circuit pulls up the reference voltage toward the supply voltage as the supply increases, thereby increasing the gate drive on the MOS transistor. The circuit provides compensation for both AC and DC supply variations. The MOS transistor is used to modulate the available current sinking capability in an IC device output buffer, such that as the MOS gate drive increases, the current sinking capability is reduced, thereby slowing the output state transitions as the supply increases, and reducing noise caused by supply variations.