Abstract: A method and apparatus for processing packetized data spanning multiple clock cycles includes at least one comparator, for comparing a present clock cycle count to a reference clock cycle count, wherein the reference clock cycle values may be anywhere within the packet and may be non-contiguous with other reference clock cycle values. At least one word recognizer, compares a presently clocked word to a reference word, and an output circuit provides an indication of a favorable word comparison that occurred in response to a favorable clock cycle count comparison.

Abstract: A word recognizer for providing a channel-to-channel compare for an input digital signal divides channels of the input digital signal into equal-width input signal channel paths. One input signal channel path serves as a reference value for comparison with the other input signal channel path to produce the channel-to-channel compare.