Patents by Inventor David Hom
David Hom has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12314605Abstract: Dynamic memory area configuration includes designating a portion of memory as a specialized memory unit, and reserving a first portion of specialized memory unit for a plurality of page frame table entries (PFTEs) representing a plurality of frames in the specialized memory. One or more of the PFTEs are stored in respective queue entries within a queue in a reserved area of the specialized memory unit. A particular queue entry indicates that a particular PFTE associated with a particular frame is available for use. An offline request to take a second portion of the specialized memory unit offline is received. Whether to fulfill the offline request is determined based on whether the second portion of the specialized memory unit has an associated queue entry within the queue indicating that the associated frame is not in use back a portion of a page frame table (PFT) or the specialized memory unit.Type: GrantFiled: March 10, 2023Date of Patent: May 27, 2025Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harris M. Morgenstern, David Hom, Robert Miller, Jr.
-
Publication number: 20250004836Abstract: Providing dedicated memory assignments to applications is disclosed, including defining an area of dedicated memory within system memory, wherein frames of the dedicated memory are assignable to one or more programs; determining, in response to a program initializing, an amount of dedicated memory to assign to the program based on a dedicated memory parameter for the program; and assigning, based on the determined amount of dedicated memory, a portion of dedicated memory to the program, wherein the assigned portion of dedicated memory is dedicated to the program until program completion.Type: ApplicationFiled: June 27, 2023Publication date: January 2, 2025Inventors: HARRIS M. MORGENSTERN, ROBERT MILLER, JR., DAVID HOM, ELPIDA TZORTZATOS, SCOTT BALLENTINE, STEVEN M. PARTLOW, DIETER WELLERDIEK, CHRISTOPHER LEE WOOD, NICHOLAS C. MATSAKIS
-
Publication number: 20240302995Abstract: Dynamic memory area configuration includes designating a portion of memory as a specialized memory unit, and reserving a first portion of specialized memory unit for a plurality of page frame table entries (PFTEs) representing a plurality of frames in the specialized memory. One or more of the PFTEs are stored in respective queue entries within a queue in a reserved area of the specialized memory unit. A particular queue entry indicates that a particular PFTE associated with a particular frame is available for use. An offline request to take a second portion of the specialized memory unit offline is received. Whether to fulfill the offline request is determined based on whether the second portion of the specialized memory unit has an associated queue entry within the queue indicating that the associated frame is not in use back a portion of a page frame table (PFT) or the specialized memory unit.Type: ApplicationFiled: March 10, 2023Publication date: September 12, 2024Inventors: HARRIS M. MORGENSTERN, DAVID HOM, ROBERT MILLER, JR.
-
Patent number: 10942683Abstract: Technical solutions are described for reducing page invalidation broadcasts in a computer system. An example method includes pre-allocating a pool of large memory frames by a real storage manager. The method also includes receiving, by a virtual storage manager, an instruction from an application to allocate a memory buffer, where the instruction includes a request to back the memory buffer using large pages. The virtual storage manager, in response to the instruction, allocates the memory buffer from the pre-allocated pool of large memory frames.Type: GrantFiled: October 28, 2015Date of Patent: March 9, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Hom, James H. Mulder, Paula M. Spens, Elpida Tzortzatos
-
Patent number: 10705983Abstract: Embodiments are provided for implementing a transparent conversion of common virtual storage requests to storage with limited access. Embodiments include providing a storage manager configured to perform address translation for requests, providing a data address translation (DAT) structure configured to connect a higher-level DAT table to a lower-level DAT table, and creating the DAT structure based on a request from a process. Embodiments also include responsive to receiving a storage request, performing a DAT fault process based on validating user credentials associated with an entry of the higher-level DAT table corresponding to the storage request, and responsive to the validation, updating the higher-level DAT table entry to allow access to the restricted-use portion of the common virtual storage, and otherwise, returning a DAT fault for the higher-level DAT table entry.Type: GrantFiled: March 1, 2019Date of Patent: July 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Elpida Tzortzatos, Michael Gary Spiegel, Karl David Schmitz, Steven Partlow, Harris M. Morgenstern, David Hom, Peter Fatzinger
-
Publication number: 20180314557Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.Type: ApplicationFiled: September 4, 2015Publication date: November 1, 2018Inventors: David Hom, Charles E. Mari, Robert J. Miller, JR., Harris M. Morgenstern, Elpida Tzortzatos
-
Patent number: 10114853Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.Type: GrantFiled: September 4, 2015Date of Patent: October 30, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Hom, Charles E. Mari, Robert J. Miller, Jr., Harris M. Morgenstern, Elpida Tzortzatos
-
Patent number: 10108466Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.Type: GrantFiled: June 29, 2015Date of Patent: October 23, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Hom, Charles E. Mari, Robert Miller, Jr., Harris M. Morgenstern, Elpida Tzortzatos
-
Patent number: 10061518Abstract: In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.Type: GrantFiled: November 29, 2017Date of Patent: August 28, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Hom, Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
-
Publication number: 20180074706Abstract: In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.Type: ApplicationFiled: November 29, 2017Publication date: March 15, 2018Inventors: David Hom, Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
-
Patent number: 9898198Abstract: In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.Type: GrantFiled: June 12, 2015Date of Patent: February 20, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Hom, Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
-
Patent number: 9715349Abstract: Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.Type: GrantFiled: March 14, 2016Date of Patent: July 25, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Hom, Paula M. Spens, Scott B. Tuttle, Elpida Tzortzatos
-
Patent number: 9703501Abstract: Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.Type: GrantFiled: September 30, 2015Date of Patent: July 11, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Hom, Paula M. Spens, Scott B. Tuttle, Elpida Tzortzatos
-
Publication number: 20170123735Abstract: Technical solutions are described for reducing page invalidation broadcasts in a computer system. An example method includes pre-allocating a pool of large memory frames by a real storage manager. The method also includes receiving, by a virtual storage manager, an instruction from an application to allocate a memory buffer, where the instruction includes a request to back the memory buffer using large pages. The virtual storage manager, in response to the instruction, allocates the memory buffer from the pre-allocated pool of large memory frames.Type: ApplicationFiled: October 28, 2015Publication date: May 4, 2017Inventors: DAVID HOM, JAMES H. MULDER, PAULA M. SPENS, ELPIDA TZORTZATOS
-
Publication number: 20170090809Abstract: Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.Type: ApplicationFiled: March 14, 2016Publication date: March 30, 2017Inventors: David Hom, Paula M. Spens, Scott B. Tuttle, Elpida Tzortzatos
-
Publication number: 20170090808Abstract: Technical solutions for providing real time analytics of a private area of a virtual address space are described. One general aspect includes a method that includes determining, by a processor, a start address and a size of the private area of the virtual address space. The method also includes determining, by the processor, a highest address corresponding to a user region of the private area. The method also includes determining, by the processor, a lowest address corresponding to a high-end region of the private area. The method also includes storing, by the processor, the determined information in a common area outside the virtual address space.Type: ApplicationFiled: September 30, 2015Publication date: March 30, 2017Inventors: David Hom, Paula M. Spens, Scott B. Tuttle, Elpida Tzortzatos
-
Publication number: 20160378572Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.Type: ApplicationFiled: June 29, 2015Publication date: December 29, 2016Inventors: David Hom, Charles E. Mari, Robert Miller, JR., Harris M. Morgenstern, Elpida Tzortzatos
-
Publication number: 20160364164Abstract: In one embodiment, a computer-implemented method includes building an available frame header queue (AFHQ). The AFHQ includes one or more headers, each header including one or more frame references being no more than a maximum count of frame references. Each of the one or more frame references of each of the one or more headers refers to an available frame. A frame request is received for one or more requested frames. One or more frame references are extracted, by a computer processor, from the AFHQ in response to the frame request. The extracting includes extracting from the AFHQ one or more requested headers including the one or more frame references referring to at least a portion of the one or more requested frames.Type: ApplicationFiled: June 12, 2015Publication date: December 15, 2016Inventors: David Hom, Harris M. Morgenstern, Steven M. Partlow, Scott B. Tuttle, Elpida Tzortzatos
-
Publication number: 20160274943Abstract: A method, a computer program product, and a system for performing a batch processing are provided. The batch processing includes initializing a set of elements corresponding to a set of resources to produce an initialized group and chaining the initialized group to previously initialized elements to produce an element batch, when the previously initialized elements are available. The batch processing further includes setting a system lock on the set of resources after the element batch is produced; executing a service routine to move the element batch to a queue by referencing first and last elements of the element batch; and releasing the system lock on the set of resources once the service routine is complete.Type: ApplicationFiled: September 4, 2015Publication date: September 22, 2016Inventors: David Hom, Charles E. Mari, Robert J. Miller, JR., Harris M. Morgenstern, Elpida Tzortzatos
-
Patent number: 9251091Abstract: A computer system includes a translation look-aside (TLB) buffer and a processing unit. The TLB is configured to store an entry that comprises virtual address information, real address information associated with the virtual address information, and additional information corresponding to at least one of the virtual address information and the real address information. The processing unit is configured to control the TLB to modify the additional information while maintaining the entry in a valid state accessible by the processing unit for a translation look-aside operation corresponding to the virtual address information and the real address information.Type: GrantFiled: June 15, 2012Date of Patent: February 2, 2016Assignee: International Business Machines CorporationInventors: David Hom, Paula M. Spens, Scott B. Tuttle, Elpida Tzortzatos