Abstract: A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed ±2? radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates and flip-flops.

Abstract: Phase-reset circuits provide first and second frequency-divided input signals to a phase/frequency detector (PFD) used in a phase-locked loop (PLL). The phase-reset circuits receive first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD generates control signals based on the phase difference between the frequency-divided input signals. Normally, the phase-reset circuits frequency divide the first and second input signals using divisors N and M, respectively. If other circuitry detects that the PFD has missed a clock cycle in the first or second clock-divided input signals, the corresponding phase-reset circuit alters its divider so that the next clock edge on the corresponding input signal clocks through to the PFD. This causes the PFD to quickly set its affected control signal to what it would have been had the clock cycle not been missed.

Abstract: A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed ±2&pgr; radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates and flip-flops.

Abstract: Phase-reset circuits provide first and second frequency-divided input signals to a phase/frequency detector (PFD) used in a phase-locked loop (PLL). The phase-reset circuits receive first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD generates control signals based on the phase difference between the frequency-divided input signals. Normally, the phase-reset circuits frequency divide the first and second input signals using divisors N and M, respectively. If other circuitry detects that the PFD has missed a clock cycle in the first or second clock-divided input signals, the corresponding phase-reset circuit alters its divider so that the next clock edge on the corresponding input signal clocks through to the PFD. This causes the PFD to quickly set its affected control signal to what it would have been had the clock cycle not been missed.