Abstract: A 3D rendered image of a radar-scanned terrain surface is provided from a radar return signal from the surface, wherein the return signal includes data indicative of azimuth, elevation, and range of a radar-illuminated area of the surface. The data are processed for transformation into X, Y, and Z coordinates. The X and Y coordinates corresponding to each illuminated area are triangulated so as to create a mesh of triangles representing the terrain surface, each of the triangles in the mesh being defined by a vertex triplet. 3D imaging information (grey scale shading and/or coloring information) is added to each triangle in the mesh, based on the amplitude of the radar return signal from the coordinates represented by each vertex in the triplet and the value of the Z coordinate at each vertex, so as to form the 3D rendered image.

Abstract: The objective of this invention is to ensure that programs that generate and send data packets are well behaved. This invention discloses a method and system that consist of an end station and a network interface, such that, the network interface is capable of determining the authenticity of the program used by the end station to generate and send data packets. The method is based on using a hidden program that was obfuscated within the program that is used to generate and send data packets from the end station. The hidden program is being updated dynamically and it includes the functionality for generating a pseudo random sequence of security signals. Only the network interface knows how the pseudo random sequence of security signals were generated, and therefore, the network interface is able to check the validity of the pseudo random sequence of security signals, and thereby, verify the authenticity of the programs used to generate and send data packets.

Abstract: A system and method of compensating for effects of on-chip processing variation on an integrated circuit. The integrated circuit is divided into a set of regions. Then, a region control logic, included in each region, predicts a processing variation in each respective region of the integrated circuit. Finally, each region control logic automatically selects one of a set of available power settings to power each one of the respective regions, in response to the region control logic predicting the processing variation, wherein the processing variation of each of the set of regions is minimized.

Abstract: A safety switch plunger includes a moveable conductor which extends transversely through the plunger and protrudes from opposite sides of the plunger. The plunger is provided with a structure that is positionally fixed on the plunger. The structure is positioned such that it is arranged to come into physical contact with and affect the movement of the moveable conductor when the moveable conductor and plunger are moved relative to one another thereby providing a fail-to-safe safety switch.

Abstract: A safety switch that includes a locking mechanism having a rod locking element that is located adjacent to a rod and engageable with the rod to lock the rod in position relative to a housing. The safety switch locking mechanism includes a locking member that is moveable relative to the housing in response to a difference in inertia between the locking member and the housing when a force is applied to the housing. The locking member is arranged to inhibit disengagement of the rod-locking element from the rod when the force is applied to the housing.

Abstract: A method of surface pasteurizing precooked food products which are contained in packages. The method preferably comprises the steps of continuously heating the packages of the precooked food product such that the outer surfaces of the products contained within the packages are taken to an effective pasteurization temperature and then continuously cooling the packages of product. The heating and cooling steps are preferably conducted in a manner such that no more than a 10° temperature increase and preferably substantially no temperature increase occurs in the internal core of the product as a result of the heating step.

Abstract: A dialysis machine includes: a hardware unit including at least one pump actuator, at least one valve actuator and a cassette interface, the cassette interface including: (i) a plate that abuts the cassette; (ii) at least one pump aperture defined by the plate; (iii) at least one pump head moveable out of and retractable into the at least one pump aperture to operate a pumping portion of the cassette; (iv) at least one valve aperture defined by the plate; (v) at least one valve apparatus moveable out of and retractable into the at least one valve aperture to operate a valve portion of the cassette; (vi) at least one sensor aperture defined by the plate; and (vii) at least one sensor located in the least one sensor aperture, the at least one sensor operable with a sensor portion of the cassette.

Abstract: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12.5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2.0 fF/um2.

Abstract: A method of sanitizing a drain having a drain conduit with a drain trap therein and an improved floor drain for use in the method of sanitizing. The method comprises the steps of (a) temporarily blocking the drain conduit at a position downstream of the trap and (b) at least partially back-filling the drain upstream of the blocked position with a sanitizing fluid.

Abstract: Leakage current from a circuit for handling data is reduced using leakage control circuit operable in a leakage reduction mode. The data handling circuit comprises data handling logic operable to receive an input data value and to output and output data value. The data handling circuit also comprises a latch operable to latch the output data value in response to a clock signal having a clock period. Both the leakage control circuitry and the latch are controlled dependent upon the same clock signal and the leakage control circuitry is controlled such that it is in a leakage reduction mode for a time less than the clock period. This approach enables leakage reduction to be provided in circuits which are still operational and is particularly suited to data handling circuits that employ frequency scaling.

Abstract: A supply switch circuit is provided for implementing a switchable on-chip high voltage supply. A stack of transistors is coupled between an on-chip high voltage supply and a circuit node. A control signal is coupled to the stack of transistors for selectively switching the high voltage supply to the circuit node. The control signal is coupled to a voltage divider included with the stack of transistors to limit a maximum node voltage within the stack of transistors.

Abstract: The present invention provides systems, methods and apparatuses for medical fluid delivery systems that employ a pumping cassette. In particular, the present invention provides systems, methods and apparatuses for cassette-based dialysis therapies including hemodialysis, hemofiltration, APD (including tidal modalities) and CFPD. The embodiments described include a combined pump/valve housing, a fail safe pump/valve arrangement, a cassette auto-alignment feature, a pumping membrane material, a multiplexing valve arrangement, an expert fluid pumping management system, an integral port vent and an in-line air separation chamber and combinations of each of these.

Abstract: A method for fabricating an NPN bipolar transistor comprises forming a base layer on a top surface of a substrate. The NPN bipolar transistor may be an NPN silicon-germanium heterojunction bipolar transistor. The method for fabricating the NPN bipolar transistor may further comprise a cap layer situated over the base layer. According to this embodiment, the method for fabricating the NPN bipolar transistor further comprises fabricating an emitter over the base layer, where the emitter defines an intrinsic and an extrinsic base region of the base layer. The emitter may comprise, for example, polycrystalline silicon. The method for fabricating the NPN bipolar transistor further comprises implanting germanium in the extrinsic base region of the base layer so as to make the extrinsic base region substantially amorphous. The method for fabricating the NPN bipolar transistor further comprises implanting boron in the extrinsic base region of the base layer.

Abstract: A portable saw has a depth or blade lowering control and an adjustable stop for selecting the maximum depth of the blade to which the blade can be lowered.

Abstract: A method, and apparatus are provided for controlling transition rates on adjacent interconnects in an electronic chip design. Each interconnect includes a first inverter that receives a net input and provides an initial inverted output and a second inverter coupled to the first inverter receiving the initial inverted output and providing a net output. A first compensating logic transistor stack coupled to the first inverter and a first adjacent net receives the initial inverted output and the first adjacent net input for selectively providing conductive paths. A second compensating logic transistor stack coupled to the first inverter and a second adjacent net receiving the initial inverted output and the second adjacent net input for selectively providing conductive paths.

Abstract: According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a high-k dielectric layer comprising AlNX (aluminum nitride) on the first interconnect layer. The method further includes depositing a layer of MIM capacitor metal on the high-k dielectric layer. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the first interconnect metal layer, the high-k dielectric layer, and the layer of MIM capacitor metal can be deposited in a PVD process chamber. The method further includes etching the high-k dielectric layer to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor.

Abstract: A saw table apparatus comprises a table and a saw mounting structure. The table includes a base and a tabletop attached to the base. The tabletop has a work-piece support surface. The saw mounting structure is engaged with the tabletop. The saw mounting structure is configured for having a hand-held circular saw attached thereto such that, when the saw mounting structure is in a use position with respect to the tabletop, a blade of the hand-held circular saw extends above a work-piece support surface of the tabletop and a work-piece engagement surface of the saw mounting structure lies substantially flush with the work-piece support surface of the tabletop. An engagement portion of the electrical plug receptacle is expose within an interior space of the base and a control portion of the electrical switch is exposed an exterior surface of the base.

Abstract: A method and apparatus are provided for implementing AC power dissipation control during scan operations in scannable latch designs. A scannable latch has a functional data output and a scan data output. A switching control is provided with the functional data output. The switching control is driven to prevent switching of the functional data output during at least part of the scan operations. Then the switching control is disabled enabling switching of the functional data output during functional data operations.

Abstract: Method for fabrication of on-chip inductors and related structure are disclosed. According to one embodiment, inductors are formed by patterning conductors within a certain dielectric layer in a semiconductor die. Thereafter, the entire dielectric layer in the semiconductor die is subjected to a blanket implantation or sputtering of high permeability material. According to another embodiment, a first area in a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor die includes a patterned conductor which is to be used as an inductor. The patterned conductor is also covered, for example, with photoresist. The second area, excluding the covered patterned conductor, is subjected to implantation or sputtering of high permeability material. According to yet another embodiment, a first area of a semiconductor die is covered, for example, with photoresist. A second area in the semiconductor area includes a patterned conductor which is to be used as an inductor.

Abstract: This invention provides a small lightweight glider that is hollow and made from a molded thin film material. Typically the glider is formed in the shape of a bird or a plane. The body of the glider comprises top half and a lower half, which form a hollow fuselage, a left wing and a right wing extending laterally from the fuselage. The glider also comprises a ballast weight, a stiffener, and optionally an interior skeleton. The interior of the glider is open to the outside atmosphere and requires no inflation.