Abstract: An apparatus, and a method therefore, are described, the apparatus according to one embodiment including a security manager and a plurality of clusters of processing elements. Each cluster of the plurality of clusters includes a respective plurality of processing elements. A controller of the apparatus, which may include a security manager, may be configured to control the plurality of clusters to receive a first data stream and a second data stream, control a first plurality of processing elements in a first cluster to process the first data stream using a first security protocol, and control a second plurality of processing elements in a second cluster to process the second data stream using a second security protocol.

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.

Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuity for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

Abstract: Apparatuses and methods for managing a coherent memory are described. These may include one or more algorithmic logic units (ALUs) and an input/output (IO) interface. The I/O interface may receive one or more commands and retrieve data from or write data to a memory device. Each command may contain a memory address portion associated with a memory device. The apparatus may also include a memory mapping unit and a device controller. The memory mapping unit may map the memory address to a memory portion of the memory device, and the device controller may communicate with the memory device to retrieve data from or write data to the memory device. The apparatus may be implemented as a processing element in a configurable logic block network, which may additionally include a control logic unit that receives programming instructions from an application and generate the one or more commands based on the instructions.

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.

Abstract: Apparatuses and methods for managing a coherent memory are described. These may include one or more algorithmic logic units (ALUs) and an input/output (I/O) interface. The I/O interface may receive one or more commands and retrieve data from or write data to a memory device. Each command may contain a memory address portion associated with a memory device. The apparatus may also include a memory mapping unit and a device controller. The memory mapping unit may map the memory address to a memory portion of the memory device, and the device controller may communicate with the memory device to retrieve data from or write data to the memory device. The apparatus may be implemented as a processing element in a configurable logic block network, which may additionally include a control logic unit that receives programming instructions from an application and generate the one or more commands based on the instructions.

Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.

Abstract: Methods and apparatus for dynamically adjusting performance of partitioned memory. In one embodiment, the method includes receiving one or more configuration requests for the memory device, determining whether to grant the one or more configuration requests for the memory device, in response to the determining, implementing the one or more configuration requests within the memory device and operating the memory device in accordance with the implementing. The adjusting of the performance for the partitioned memory includes one or more of enabling/disabling refresh operations, altering a refresh rate for the partitioned memory, enabling/disabling error correcting code (ECC) circuitry for the partitioned memory, and/or altering a memory cell architecture for the partitioned memory. Systems and applications that may benefit from the dynamic adjustment of performance are also disclosed.

Abstract: Methods, apparatuses, and systems for implementing data flows in a processor are described herein. A data flow manager may be configured to generate a configuration packet for a compute operation based on status information regarding multiple processing elements of the processor. Accordingly, multiple processing elements of a processor may concurrently process data flows based on the configuration packet. For example, the multiple processing elements may implement a mapping of processing elements to memory, while also implementing identified paths, through the processor, for the data flows. After executing the compute operation at certain processing elements of the processor, the processing results may be provided. In speech signal processing operations, the processing results may be compared to phonemes to identify such components of human speech in the processing results.

Abstract: An apparatus in a configurable logic unit may include a configurable logic unit (CLU) configured to receive first and second operands and to perform an operand operation and generate an operation value. The apparatus may also include: a random value generator for generating a random value; an adder coupled to the CLU and the random value generator and configured to generate a sum of the operation value and the random value; and a shift register coupled to the adder and configured to shift the sum by a number of bits to generate shifted data at an output. The random value generator may be a linear feedback shift register. The output may be coupled to an additional CLU so that the shifted data may be used for subsequent operand operations. The apparatus may be implemented in a digital signal processor slice in a configurable logic block.

Abstract: A device comprising a plurality of antennas operable to transmit and receive communication packets via a plurality of communication protocols and an integrated circuit chip coupled to the plurality of antennas. The integrated circuit chip comprises a first and a second plurality of processing elements. The first plurality of processing elements operable to receive communication packets via a first one of a plurality of communication protocols and process an optimal route. The second plurality of processing elements communicatively coupled to the first plurality of processing elements and operable to determine the optimal route to transmit the communication packets from a source device to a destination device based, at least in part, on transmission characteristics associated with at least one of the source or destination devices.

Abstract: An apparatus, and a method therefore, are described, the apparatus according to one embodiment including a security manager and a plurality of clusters of processing elements. Each cluster of the plurality of clusters includes a respective plurality of processing elements. A controller of the apparatus, which may include a security manager, may be configured to control the plurality of clusters to receive a first data stream and a second data stream, control a first plurality of processing elements in a first cluster to process the first data stream using a first security protocol, and control a second plurality of processing elements in a second cluster to process the second data stream using a second security protocol.

Abstract: An apparatus in a configurable logic unit may include a configurable logic unit (CLU) configured to receive first and second operands and to perform an operand operation and generate an operation value. The apparatus may also include: a random value generator for generating a random value; an adder coupled to the CLU and the random value generator and configured to generate a sum of the operation value and the random value; and a shift register coupled to the adder and configured to shift the sum by a number of bits to generate shifted data at an output. The random value generator may be a linear feedback shift register. The output may be coupled to an additional CLU so that the shifted data may be used for subsequent operand operations. The apparatus may be implemented in a digital signal processor slice in a configurable logic block.

Abstract: Apparatuses and methods for managing a coherent memory are described. These may include one or more algorithmic logic units (ALUs) and an input/output (IO) interface. The I/O interface may receive one or more commands and retrieve data from or write data to a memory device. Each command may contain a memory address portion associated with a memory device. The apparatus may also include a memory mapping unit and a device controller. The memory mapping unit may map the memory address to a memory portion of the memory device, and the device controller may communicate with the memory device to retrieve data from or write data to the memory device. The apparatus may be implemented as a processing element in a configurable logic block network, which may additionally include a control logic unit that receives programming instructions from an application and generate the one or more commands based on the instructions.

Abstract: A device comprising a plurality of antennas operable to transmit and receive communication packets via a plurality of communication protocols and an integrated circuit chip coupled to the plurality of antennas. The integrated circuit chip comprises a first and a second plurality of processing elements. The first plurality of processing elements operable to receive communication packets via a first one of a plurality of communication protocols and process an optimal route. The second plurality of processing elements communicatively coupled to the first plurality of processing elements and operable to determine the optimal route to transmit the communication packets from a source device to a destination device based, at least in part, on transmission characteristics associated with at least one of the source or destination devices.

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.