Patents by Inventor David Hurley

David Hurley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250120154
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a first deposition chamber of a manufacturing platform, the semiconductor wafer comprising a first conductive layer, depositing a dielectric layer on the first conductive layer in the first deposition chamber, placing the semiconductor wafer in a second deposition chamber of the manufacturing platform, and depositing a second conductive layer on the dielectric layer in the second deposition chamber. The method further includes placing the semiconductor wafer into a processing chamber of an electric-field annealer of the manufacturing platform, and in the processing chamber, applying an electrical bias voltage across the dielectric layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential, and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Application
    Filed: December 20, 2024
    Publication date: April 10, 2025
    Inventors: Dina H. Triyoso, Robert D. Clark, David Hurley, Ian Colgan
  • Patent number: 12235045
    Abstract: The disclosure describes equipment for magnetic annealing of a substrate, the equipment including: an anneal chamber configured to heat and cool a substrate held at a soak location along a first direction in the anneal chamber, the anneal chamber including: a heater, a cooler, and a substrate lifter including a substrate holder, where the substrate holder is configured to support a substrate oriented such that the first direction is perpendicular to a major surface of the substrate; and a magnet assembly configured to establish a homogeneous zone in the anneal chamber, the soak location being within the homogeneous zone, the homogeneous zone including a region of magnetic field.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: February 25, 2025
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Ian Colgan, Ioan Domsa, George Eyres, Bartlomiej Burkowicz, Barry Clarke, David Hurley, Einstein Noel Abarra
  • Patent number: 12211907
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a first deposition chamber of a manufacturing platform, the semiconductor wafer comprising a first conductive layer, depositing a dielectric layer on the first conductive layer in the first deposition chamber, placing the semiconductor wafer in a second deposition chamber of the manufacturing platform, and depositing a second conductive layer on the dielectric layer in the second deposition chamber. The method further includes placing the semiconductor wafer into a processing chamber of an electric-field annealer of the manufacturing platform, and in the processing chamber, applying an electrical bias voltage across the dielectric layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential, and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: January 28, 2025
    Assignee: Tokyo Electron Limited
    Inventors: Dina H. Triyoso, Robert D. Clark, David Hurley, Ian Colgan
  • Patent number: 11894240
    Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: February 6, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson, Gerrit J. Leusink, Robert Clark, Dina Triyoso
  • Patent number: 11837652
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: December 5, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson
  • Publication number: 20230304741
    Abstract: The disclosure describes equipment for magnetic annealing of a substrate, the equipment including: an anneal chamber configured to heat and cool a substrate held at a soak location along a first direction in the anneal chamber, the anneal chamber including: a heater, a cooler, and a substrate lifter including a substrate holder, where the substrate holder is configured to support a substrate oriented such that the first direction is perpendicular to a major surface of the substrate; and a magnet assembly configured to establish a homogeneous zone in the anneal chamber, the soak location being within the homogeneous zone, the homogeneous zone including a region of magnetic field.
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Inventors: Ian Colgan, Ioan Domsa, George Eyres, Bartlomiej Burkowicz, Barry Clarke, David Hurley, Einstein Noel Abarra
  • Patent number: 11549910
    Abstract: A method and apparatus for measuring multiple parameters of drilling fluid using electric field perturbation, permittivity curves, time domain analysis and frequency domain analysis to identify constituents of drilling fluid and ratios of the drilling fluid constituents on a real time basis and to measure volumes and densities of the constituents on a real time basis.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: January 10, 2023
    Assignee: Mohr and Associates
    Inventors: Charles L. Mohr, Brandt C. Mohr, Benno Mohr, Michael Stordahl, James Van Corbach, Erik Von Reis, Christopher Mulkey, Ryan Sams, Kevin Dawes, Preston May, Duan Nguyen, Gordon Anderson, Dan Kenney, Bill Rausch, David Hurley
  • Patent number: 11527345
    Abstract: An apparatus for magnetic annealing one or more workpieces, and a method of operating the apparatus, are described. The apparatus includes: a workpiece holder configured to support one or more workpieces, wherein the one or more workpieces having at least one substantially planar surface; an optional workpiece heating system configured to elevate the one or more workpieces to an anneal temperature; and a magnet assembly having a first magnet and a second magnet, the first and second magnets defining a gap between opposing poles of each magnet, wherein the magnet assembly is arranged to generate a magnetic field substantially perpendicular to the planar surface of the one or more workpieces.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: December 13, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Ian Colgan, Ioan Domsa, George Eyres, Toru Ishii, Makoto Saito, David Hurley, Noel O'Shaughnessy, Barry Clarke, Gerhardus Van Der Linde, Pat Hughes
  • Publication number: 20220262921
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 18, 2022
    Inventors: David Hurley, Ioan Domsa, lan Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson
  • Patent number: 11335792
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 17, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson
  • Patent number: 11262323
    Abstract: A method for identifying and characterizing a condensate entrained in a fluid using time domain analysis and frequency domain analysis to identify individual volume fraction constituents and condensates within a pipe on a real time basis and to measure the volume of the individual volume fraction constituents and condensates flowing through the pipe on a real time basis.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: March 1, 2022
    Assignee: Mohr and Associates
    Inventors: Charles L. Mohr, Brandt C. Mohr, Benno Mohr, Michael Stordahl, Anthony Cottam, Erik Von Reis, Christopher Mulkey, Ryan Sams, Kevin Dawes, Preston May, Duan Nguyen, Daniel Kenney, William Rausch, David Hurley
  • Publication number: 20210367046
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a first deposition chamber of a manufacturing platform, the semiconductor wafer comprising a first conductive layer, depositing a dielectric layer on the first conductive layer in the first deposition chamber, placing the semiconductor wafer in a second deposition chamber of the manufacturing platform, and depositing a second conductive layer on the dielectric layer in the second deposition chamber. The method further includes placing the semiconductor wafer into a processing chamber of an electric-field annealer of the manufacturing platform, and in the processing chamber, applying an electrical bias voltage across the dielectric layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential, and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Dina H. Triyoso, Robert D. Clark, David Hurley, Ian Colgan
  • Publication number: 20210313444
    Abstract: A method of fabricating a semiconductor device includes placing a semiconductor wafer into a processing chamber, the semiconductor wafer including a first conductive layer and a second conductive layer separated by an intermediate layer; applying an electrical bias voltage across the intermediate layer by coupling the first conductive layer to a first potential and coupling the second conductive layer to a second potential; and annealing the semiconductor wafer while applying the electrical bias voltage.
    Type: Application
    Filed: April 6, 2020
    Publication date: October 7, 2021
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson
  • Publication number: 20210313189
    Abstract: A system for processing semiconductor wafers, the system including: a processing chamber; a heat source; a substrate holder configured to expose a semiconductor wafer to the heat source; a first electrode configured to be detachably coupled to a first major surface of a semiconductor wafer; and a second electrode coupled to the substrate holder, the first electrode and the second electrode together configured to apply an electric field in the semiconductor wafer.
    Type: Application
    Filed: February 25, 2021
    Publication date: October 7, 2021
    Inventors: David Hurley, Ioan Domsa, Ian Colgan, Gerhardus Van Der Linde, Patrick Hughes, Maciej Burel, Barry Clarke, Mihaela Ioana Popovici, Lars-Ake Ragnarsson, Gerrit J. Leusink, Robert Clark, Dina Triyoso
  • Publication number: 20200232090
    Abstract: A substrate processing device and a processing system process substrates each having a magnetic layer individually and are provided with: a support unit for supporting a substrate; a heating unit for heating the substrate supported on the support unit; a cooling unit for cooling the substrate supported on the support unit; a magnet unit for generating a magnetic field; and a processing chamber accommodating the support unit, the heating unit, and the cooling unit. The magnet unit includes a first and a second end surface which extend in parallel. The first and the second end surface are opposite to each other while being spaced apart from each other. The first end surface corresponds to a first magnetic pole of the magnet unit. The second end surface corresponds to a second magnetic pole of the magnet unit. The processing chamber is disposed between the first and the second end surface.
    Type: Application
    Filed: February 21, 2018
    Publication date: July 23, 2020
    Inventors: Hiroki MAEHARA, Naoki WATANABE, Toru ISHII, Kanto NAKAMURA, Makoto SAITO, David HURLEY, Ian COLGAN
  • Publication number: 20200166478
    Abstract: A method and apparatus for measuring multiple parameters of drilling fluid using electric field perturbation, permittivity curves, time domain analysis and frequency domain analysis to identify constituents of drilling fluid and ratios of the drilling fluid constituents on a real time basis and to measure volumes and densities of the constituents on a real time basis.
    Type: Application
    Filed: May 9, 2018
    Publication date: May 28, 2020
    Inventors: Charles L. MOHR, Brandt C. MOHR, Benno MOHR, Michael STORDAHL, James VAN CORBACH, Erik VON REIS, Christopher MULKEY, Ryan SAMS, David HURLEY, Gordon ANDERSON, Daniel KENNY, William RAUSCH, Kevin DAWES, Preston MAY, Duan NGUYEN
  • Publication number: 20190371506
    Abstract: An apparatus for magnetic annealing one or more workpieces, and a method of operating the apparatus, are described. The apparatus includes: a workpiece holder configured to support one or more workpieces, wherein the one or more workpieces having at least one substantially planar surface; an optional workpiece heating system configured to elevate the one or more workpieces to an anneal temperature; and a magnet assembly having a first magnet and a second magnet, the first and second magnets defining a gap between opposing poles of each magnet, wherein the magnet assembly is arranged to generate a magnetic field substantially perpendicular to the planar surface of the one or more workpieces.
    Type: Application
    Filed: January 3, 2018
    Publication date: December 5, 2019
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Ian COLGAN, Ioan DOMSA, George EYRES, Toru ISHII, Makoto SAITO, David HURLEY, Noel O'SHAUGHNESSY, Barry CLARKE, Jattie VAN DER LINDE, Pat HUGHES
  • Publication number: 20190011385
    Abstract: A method for identifying and characterizing a condensate entrained in a fluid using time domain analysis and frequency domain analysis to identify individual volume fraction constituents and condensates within a pipe on a real time basis and to measure the volume of the individual volume fraction constituents and condensates flowing through the pipe on a real time basis.
    Type: Application
    Filed: September 14, 2018
    Publication date: January 10, 2019
    Inventors: Charles L. Mohr, Brandt C. Mohr, Benno Mohr, Michael Stordahl, Anthony Cottam, Erik Von Reis, Christopher Mulkey, Ryan Sams, Kevin Dawes, Preston May, Duan Nguyen, Daniel Kenney, William Rausch, David Hurley
  • Patent number: 10119929
    Abstract: A method for identifying and measuring volume fraction constituents of a fluid using time domain analysis and frequency domain analysis to identify individual volume fraction constituents within a pipe on a real time basis and to measure the volume of the individual volume fraction constituents flowing through the pipe on a real time basis.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 6, 2018
    Assignee: Mohr and Associates
    Inventors: Charles L. Mohr, Brandt C. Mohr, Benno Mohr, Michael Stordahl, James Van Corbach, Erik Von Reis, Christopher Mulkey, Ryan Sams, David Hurley, Gordon Anderson, Daniel Kenney, William Rausch, Edgar Gilbert
  • Patent number: 10119850
    Abstract: An apparatus for identifying and measuring volume fraction constituents of a fluid using time domain analysis and frequency domain analysis to identify individual volume fraction constituents within a pipe on a real time basis and to measure the volume of the individual volume fraction constituents flowing through the pipe on a real time basis.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: November 6, 2018
    Assignee: Mohr and Associates
    Inventors: Charles L. Mohr, Brandt C. Mohr, Benno Mohr, Michael Stordahl, James Van Corbach, Erik Von Reis, Christopher Mulkey, Ryan Sams, David Hurley, Gordon Anderson, Daniel Kenney, William Rausch, Edgar Gilbert