Abstract: A method of providing access to an input/output (I/O)-mapped register of a computer system is described. The computer system includes a processor operable in a system management mode (SMM), in which the processor accesses a dedicated system management memory space, a real mode, a protected mode and a virtual 8086 mode. The method includes the steps of firstly receiving an access request at the I/O-mapped register. Logic circuitry associated with the I/O-mapped register then determines whether the processor is operating in SMM by examining the status of a system management interrupt acknowledge (SMIACT#) output of the processor. If the logic circuitry determines that the processor is operating in SMM, a first, unrestricted type of access by the processor to the I/O-mapped register is provided. Alternatively, if the logic circuitry determines that the processor is not operating in SMM, a second, restricted type of access by the processor to the I/O-mapped register is provided.

Abstract: An apparatus and method for coordinating DMA between memory and a peripheral on a bus which does not support DMA comprises DMA emulation circuitry in the peripheral which allows the internal modules of the peripheral to share a single shared interrupt output line. An emulation device driver assists the microprocessor in determining the cause of interrupt signals received by the shared interrupt output line and how to service the interrupt.

Abstract: A computer system that implements a direct memory access (DMA) request passing protocol. The computer system may comprise a Peripheral Component Interconnect (PCI) bus that includes an electrical interface as specified by a PCI Local Bus standard. The PCI bus is coupled to at least one DMA agent and a DMA controller. The DMA agent issues DMA requests to the DMA controller using the electrical interface of the PCI bus. According to one embodiment, a system I/O controller receives the DMA requests and passes them on to the DMA controller, which arbitrates the DMA requests and passes back a grant to the system I/O controller. The system I/O controller uses the electrical interface of the PCI bus to pass the grant to the DMA agent. The same DMA request passing protocol may be implemented in any bus having an electrical interface that specifies a unique request signal line for each bus agent of the bus.

Abstract: A digital system bus and its attached devices can be powered down and up using only its standard bus request and bus grant signal lines, without adding additional lines for control signals. By asserting the bus grant signal in the absence of the bus request signal, the bus arbiter device can signal other devices on the bus that is okay to enter a deep power conservation mode. In this mode, the devices on the bus may safely ignore bus activity--except they must monitor for a negation of the bus grant signal or for any system wake-up events for which they are responsible. Substantial power reduction can be achieved in such a mode, since clocks can be suspended to a large portion of the circuitry in the computer system. To wake up the non-arbiter devices, the bus arbiter simply negates the bus grant signal. To wake up the bus arbiter device, a non-arbiter device simply asserts its bus request signal.