Abstract: An image compression and expansion processor includes a dual port memory configured with image and compressed data processing blocks, a host processor for managing movement of predefined blocks of data between an external frame store memory and the dual port memory, and a digital signal processor for compressing or expanding the data stored in the dual port memory. Because minimum redundancy encoding and decoding is employed to reduce the data stream according to the complexity of the image, data streams of undefined length (relative to the predefined blocks of data) are periodically resident in the compressed processing block. By maintaining bit length definition of the data in the compressed block (relative to the predefined blocks), the host processor is able to move defined lengths of compressed data from the dual port memory while the digital signal processor is concurrently processing the predefined blocks of image data.