Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

Abstract: A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.

Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

Abstract: A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.

Abstract: A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.

Abstract: A semiconductor device having a plurality of layers and a plurality of circuit elements arranged in tiles. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections of the plurality of circuit elements. The semiconductor device may include an interconnection quilt having a plurality of metal layers disposed to interconnect the plurality of circuit elements. The plurality of circuit elements may be analog circuit element and/or digital circuit elements. The tiles may be analog tiles and digital tiles that form a mixed signal structured array.

Abstract: A semiconductor device having a plurality of layers and a capacitor array that includes a plurality of individual capacitors. At least one of the plurality of layers in the semiconductor device may be a via layer configured to determine the connections and capacitances of the plurality of individual capacitors in the capacitor array. The semiconductor device may include a metal structure disposed within the device to provide an electromagnetic shield for at least one of the plurality of individual capacitors in the capacitor array.