Patents by Inventor David Isaman

David Isaman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050060619
    Abstract: A method of utilizing timestamps for the global ordering of event information, particularly hardware error reporting, is disclosed. Locally generated time stamps are associated with hardware errors or other events. The timestamps form the basis for the global ordering of event information. The timestamps are normalized, either through a pre-synchronization process with a common time, or through the use of offsets maintained either locally near system chips or by the system processor. Once normalized, the timestamps can be compared to determine a first occurring event among multiple reported events.
    Type: Application
    Filed: September 12, 2003
    Publication date: March 17, 2005
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Dean Liberty, Andrew Phelps, David Isaman
  • Publication number: 20050015778
    Abstract: A method for expressing the algorithms for the manipulation of hardware includes providing program instructions that describe a sequence of one or more transactions for manipulating hardware components of a system. The program instructions may call one or more code segments that include specific information associated with particular hardware components of the system. In addition, the program instructions are independent of the specific information. The method may also include translating the program instructions into an executable form and executing the executable form of the program instructions to manipulate the hardware components of the system from one consistent state to a next consistent state.
    Type: Application
    Filed: July 14, 2003
    Publication date: January 20, 2005
    Inventors: Douglas Meyer, David Isaman, William Jackson
  • Patent number: 6671762
    Abstract: A system and method is provided to reduce the latency associated with saving and restoring the state of the floating point registers in a microprocessor when switching tasks between floating point and MMX operations, or between tasks within the same context. The present invention maintains a secondary register file along with the primary floating point register file in the CPU. The primary register will keep the state of the floating point task “as is” upon the occurrence of a task switch to MMX, or another context. The address of the area where the FPU state is saved is maintained in a save area address register. The secondary register is then utilized by the other context to store intermediate results of executed instructions. In the majority of cases when a context switch back to floating point operations occurs, the previous state is restored from the primary register without incurring the latency of retrieving the instructions and data from the memory subsystem.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: December 30, 2003
    Assignee: STMicroelectronics, Inc.
    Inventors: Naresh H. Soni, David Isaman