Abstract: A system for transferring data packets between a data packet transfer core and a number of clients of an application layer, including an interface between the data packet transfer core and the application layer for transferring data packets from the packet transfer core to a first client and a second client. The data packet transfer core includes a number of core buffers for receiving data packet transfers input to the data packet transfer core. Each of the number of core buffers include a cut-through data path including a register and a bypass data path, the bypass data path transferring data packets from an input to the register to an output of the register without passing through the register.

Abstract: A system for controlling packet transfers includes a packet transfer core; an application layer coupled to the packet transfer core by an application interface; a buffer in the packet transfer core for receiving packets from a packet source and transferring the packets to the application layer over the application interface, the packets comprising one or more words; a register in the application layer for receiving packets from the application interface; and a client device for receiving packets transferred thereto from the register. When the client is unable to receive packets from the register, the client asserts a first wait signal to the register, causing the register to continue receiving packets from the interface and storing the packets without transferring the packets to the client.

Abstract: A system for transferring packets between a packet transfer core and an application layer device over an application layer interface includes a buffer system disposed in the packet transfer core having an input for receiving packets from a packet source; an output for transferring packets to the application layer interface; a buffer device having an input coupled to the input of the buffer system and an output; a selection device having a first input coupled to the output of the buffer device, a control input and an output coupled to the output of the buffer system; and a bypass path coupled between the input of the buffer system and a second input of the selection device. The control input of the selection device receives a first wait signal from the application layer device which is not asserted in a first mode of operation and asserted in a second mode of operation.