Patents by Inventor David J. Allstot

David J. Allstot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8432218
    Abstract: A harmonic-rejection power amplifier is disclosed. In an embodiment, the harmonic-rejection power amplifier includes a plurality of stages, each stage comprising a respective signal-generation component coupled to a respective power amplifier, wherein the respective signal-generation component is configured to output a respective signal having a respective phase, and wherein the respective power amplifier is configured to output an amplified version of the respective signal. In the harmonic-rejection power amplifier, each respective phase differs from each other respective phase by a respective amount that is predefined based on a number of stages in the plurality of stages, and the plurality of stages are coupled in parallel to a combiner configured to combine the output of each respective power amplifier into a combined output. At least one harmonic in the combined output may be at least partially rejected.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: April 30, 2013
    Assignee: University of Washington through its Center For Commercialization
    Inventors: Jacques C. Rudell, Parmoon Seddighrad, David J. Allstot
  • Patent number: 7755442
    Abstract: Embodiments of the present invention include a common-gate amplifier having an input terminal and an output terminal, a transistor having a source, a drain, and a gate, four inductors, and two capacitors, and a negative amplification circuitry. The negative amplification circuitry has an input terminal to receive an RF signal. The negative amplification circuitry applies negative or zero amplification to the RF signal and outputs the negative or zero amplified signal on an output terminal. Alternative embodiments include a Colpitts differential oscillator, which includes two Colpitts single-ended oscillators. Each Colpitts single-ended oscillator includes a transistor. The source of the transistor in one Colpitts single-ended oscillator may be capacitively coupled to the gate of the transistor in the other Colpitts single-ended oscillator.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: July 13, 2010
    Assignee: University of Washington
    Inventors: Xiaoyong Li, David J. Allstot
  • Publication number: 20080290957
    Abstract: Embodiments of the present invention include a common-gate amplifier having an input terminal and an output terminal, a transistor having a source, a drain, and a gate, four inductors, and two capacitors, and a negative amplification circuitry. The negative amplification circuitry has an input terminal to receive an RF signal. The negative amplification circuitry applies negative or zero amplification to the RF signal and outputs the negative or zero amplified signal on an output terminal. Alternative embodiments include a Colpitts differential oscillator, which includes two Colpitts single-ended oscillators. Each Colpitts single-ended oscillator includes a transistor. The source of the transistor in one Colpitts single-ended oscillator may be capacitively coupled to the gate of the transistor in the other Colpitts single-ended oscillator.
    Type: Application
    Filed: August 7, 2008
    Publication date: November 27, 2008
    Applicant: UNIVERSITY OF WASHINGTON
    Inventors: Xiaoyong Li, David J. Allstot
  • Patent number: 7414481
    Abstract: Embodiments of the present invention include a common-gate amplifier having an input terminal and an output terminal, a transistor having a source, a drain, and a gate, four inductors, and two capacitors, and a negative amplification circuitry. The negative amplification circuitry has an input terminal to receive an RF signal. The negative amplification circuitry applies negative or zero amplification to the RF signal and outputs the negative or zero amplified signal on an output terminal. Alternative embodiments include a Colpitts differential oscillator, which includes two Colpitts single-ended oscillators. Each Colpitts single-ended oscillator includes a transistor. The source of the transistor in one Colpitts single-ended oscillator may be capacitively coupled to the gate of the transistor in the other Colpitts single-ended oscillator.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: August 19, 2008
    Assignee: University of Washington
    Inventors: Xiaoyong Li, David J. Allstot
  • Patent number: 7221217
    Abstract: A differential RF non-linear power amplifier employing low-voltage transistors in a cascode configuration uses self-biasing solutions rather than external biasing techniques to overcome transistor breakdown problems. The self-biasing solution ensures that the cascode devices and driver device operate below breakdown voltage limitations. A low resistance circuit is placed in parallel with the self-biased circuitry to mitigate increased on-resistance created by the self-biasing solution. PMOS and NMOS inverter legs provide digital programming of the conduction angle for the power amplifier. Changing the PMOS and NMOS strengths in the chain of inverter legs changes the conduction angle.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: May 22, 2007
    Assignee: University of Washington
    Inventors: Kiyong Choi, David J. Allstot
  • Publication number: 20040217813
    Abstract: A differential RF non-linear power amplifier employing low-voltage transistors in a cascode configuration uses self-biasing solutions rather than external biasing techniques to overcome transistor breakdown problems. The self-biasing solution ensures that the cascode devices and driver device operate below breakdown voltage limitations. A low resistance circuit is placed in parallel with the self-biased circuitry to mitigate increased on-resistance created by the self-biasing solution. PMOS and NMOS inverter legs provide digital programming of the conduction angle for the power amplifier. Changing the PMOS and NMOS strengths in the chain of inverter legs changes the conduction angle.
    Type: Application
    Filed: June 19, 2003
    Publication date: November 4, 2004
    Inventors: Kiyong Choi, David J. Allstot
  • Patent number: 6563348
    Abstract: Methods and apparatuses for double-sampling a signal using an operational amplifier having dedicated unswitched connections to sample and hold circuits. In one embodiment, a circuit according to the teachings of the present invention includes an op-amp having four input terminals. Two of the input terminals are tied to ground and the other two terminals are coupled to S/H circuits through unswitched connections. In one embodiment, the S/H circuits are coupled to sample an input signal during different clock phases.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: May 13, 2003
    Assignee: University of Washington
    Inventors: Douglas R. Beck, David J. Allstot
  • Patent number: 5162674
    Abstract: In integrated circuitry having both analog and digital circuits fabricated on the same substrate, switching transients produced by the digital circuitry can propagate through the substrate and induce deleterious effects in the associated analog circuitry. Such switching transients are greatly minimized by the disclosed family of CMOS logic circuits in which a constant DC bias current is steered to change logic states.
    Type: Grant
    Filed: May 10, 1991
    Date of Patent: November 10, 1992
    Assignee: State of Oregon Acting by and Through the State Board of Higher Education on Behalf of Oregon State University
    Inventors: David J. Allstot, Guojin Liang, Howard C. Yang
  • Patent number: 5149992
    Abstract: In integrated circuitry having both analog and digital circuits fabricated on the same substrate, switching transients produced by the digital circuitry can propagate through the substrate and induce deleterious effects in the associated analog circuitry. Such switching transients are greatly minimized by a CMOS source-coupled current-steering differential logic topology. In the preferred embodiment, gain and level shifting functions are merged, and connections to the power bus are made through constant current sources.
    Type: Grant
    Filed: April 30, 1991
    Date of Patent: September 22, 1992
    Assignee: The State of Oregon Acting by and Through the State Board of Higher Education on Behalf of Oregon State University
    Inventors: David J. Allstot, Sayfe Kiasei