Abstract: An adaptive hysteresis receiver processes a high speed digital signal. A differential receiver circuit compares the high speed digital signal to a reference voltage to generate an output signal. A register circuit latches the output signal, according to a clock signal, to produce a control signal. A reference voltage generator generates the reference voltage, from a plurality of voltages defining a deep hysteresis level and a shallow hysteresis level, in response to the output signal and the control signal.

Abstract: A single age-bit may provided for each line in a cache, or for each index. Each time a line, or index, is accessed, or written, the corresponding age-bit is set to a first logical state. A state machine periodically checks the status of each age-bit. If an age-bit is in the first logical state, the state machine sets the age-bit to a second logical state. If the age-bit is already in the second logical state, then the line of data corresponding to the age-bit, or at least one line in the set of lines corresponding to the index corresponding to the age-bit, has not been accessed or changed since the last time the state machine checked the age-bit, and may be preemptively evicted.

Abstract: A single age-bit may provided for each line in a cache, or for each index. Each time a line, or index, is accessed, or written, the corresponding age-bit is set to a first logical state. A state machine periodically checks the status of each age-bit. If an age-bit is in the first logical state, the state machine sets the age-bit to a second logical state. If the age-bit is already in the second logical state, then the line of data corresponding to the age-bit, or at least one line in the set of lines corresponding to the index corresponding to the age-bit, has not been accessed or changed since the last time the state machine checked the age-bit.

Abstract: A first integrated circuit has a driver with the pullup and pulldown devices independently controlled. The output of the driver is connected through an impedance to one end of a transmission line. The other end of the transmission line is connected to a second integrated circuit. The second integrated circuit has a pulldown device connected to the transmission line. The first integrated circuit drives both high logic states and low logic states through the impedance to effect a series termination for communication from the first integrated circuit to the second integrated circuit. The first integrated circuit drives a high logic state through the impedance to effect a parallel termination for communication from the second integrated circuit to the first integrated circuit.