Abstract: A method and circuit for implementing calibration of a linearly weighted, thermal coded I/O driver output stage, and a design structure on which the subject circuit resides are provided. The circuit includes a PFET calibration impedance matching function determining calibration PVTP bits for calibrating output stage PFETs of the linearly weighted, thermal coded I/O driver output stage, an NFET calibration impedance matching function determining calibration bits PVTN for calibrating output stage NFETs of the linearly weighted, thermal coded I/O driver output stage once the PFET calibration is complete and an output latch function providing the calibration PVTP and PVTN outputs for the I/O driver output stage to match an impedance of an external calibration resistor. A clock logic function generates an output latch clock and an internal reset signal completing calibration.

Abstract: A method and circuit for implementing calibration of a linearly weighted, thermal coded I/O driver output stage, and a design structure on which the subject circuit resides are provided. The circuit includes a PFET calibration impedance matching function determining calibration PVTP bits for calibrating output stage PFETs of the linearly weighted, thermal coded I/O driver output stage, an NFET calibration impedance matching function determining calibration bits PVTN for calibrating output stage NFETs of the linearly weighted, thermal coded I/O driver output stage once the PFET calibration is complete and an output latch function providing the calibration PVTP and PVTN outputs for the I/O driver output stage to match an impedance of an external calibration resistor. A clock logic function generates an output latch clock and an internal reset signal completing calibration.

Abstract: Methods and apparati for controlling bleed current (IBLEED) in a driver circuit (20) for a lighting device (23). A method embodiment of the present invention comprises the steps of coupling a dimmer (21) to an input of the driver circuit (20), and forcing the bleed current (IBLEED) to be inversely proportional to the time-averaged voltage (VLEDP) at said lighting device (23). The dimmer (21) consumes power even when the lighting device (23) is not emitting light.

Abstract: Methods and apparati for forcing the current through a load (11) in a variable DC electrical circuit to be proportional to the input voltage (V(in)). A circuit embodiment of the present invention comprises a source (27) of input AC; a rectifier (23) coupled to the input AC source (27), said rectifier (23) producing a variable DC input voltage; coupled to the rectifier (23), a load (11) having a variable direct current flowing therethrough; and means (12-16) for forcing the current through the load (11) to be proportional to the variable DC input voltage.

Abstract: A voltage level translating circuit that allows low voltage signals to be translated to higher voltages, a design structure utilized in the design, manufacture, and/or testing of the voltage level translating circuit, and a method of manufacturing the voltage level translating circuit are described. The translating circuit utilizes two different voltage domains. The high voltage rail of the low voltage domain acts as the ground of the high voltage domain. The translating circuit also utilizes a voltage buffer electrically connected to the high voltage domain and to the low voltage domain to prevent the circuit devices in either domain from seeing too high of a voltage. The translating circuit allows the circuits after the translating circuit to work with signals utilizing the high voltage rail of the high voltage domain.

Abstract: A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance.

Abstract: A memory interface device, system, method, and design structure for controlling for variable impedance and voltage in a memory system are provided. The memory interface device includes a calibration cell configurable to adjust an output impedance relative to an external reference resistor, and driver circuitry including multiple positive drive circuits and multiple negative drive circuits coupled to a driver output in a memory system. The memory interface device further includes impedance control logic to adjust the output impedance of the calibration cell and selectively enable the positive and negative drive circuits as a function of a drive voltage and a target impedance.

Abstract: The identification and use of two major DNA-PKcs autophosphorylation sites. Threonine (T) 2609 and Serine (S) 2056, including antibodies specific for phosphorylated T2609 and 52056. Peptides and polynucleotides encoding same, that feature these two sites of phosphorylation. The antibodies do not bind to the unphosphorylated DNA-PKcs protein or peptide, thus providing diagnostic tools to monitor the effectiveness of treatments which target the DNA repair pathway of cancer cells, and the ability to intervene or inhibit in phosphorylation of T2609 or 52056, either through application of a drug or an antibody, to increase the radiosensitivity of cancer cells.

Abstract: A voltage level shifting device for translating a lower operating voltage to a higher operating voltage includes a first input node coupled to a first pull down device and a second input node coupled to a second pull down device. The second node receives a complementary logic signal with respect to the first input node, the first and second input nodes associated with the lower operating voltage. A first pull up device is in series with the first pull down device and second pull up device is in series with the second pull down device, with the first and second pull up devices coupled to a power supply at the higher operating voltage. An output node is between the second pull down device and the second pull up device, the output node controlling the conductivity of the first pull up device. A clamping device is in parallel with the first pull up device, and configured to prevent the second pull up device from becoming fully saturated.