Patents by Inventor David J. Chura

David J. Chura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7706361
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 [logb N] stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and [logb N] indicates a ceiling function providing the smallest integer not less than logb N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: April 27, 2010
    Assignee: Teradata US, Inc.
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Patent number: 7058084
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 ?logb N? stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and ?logb N? indicates a ceiling function providing the smallest integer not less than logb N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: June 6, 2006
    Assignee: NCR Corporation
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Publication number: 20020010735
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 [logb N] stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and [logb N] indicates a ceiling function providing the smallest integer not less than logb N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Application
    Filed: February 14, 2001
    Publication date: January 24, 2002
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Patent number: 6243361
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 |logb N| stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and |logb N| indicates a ceiling function providing the smallest integer not less than logb N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: June 5, 2001
    Assignee: NCR Corporation
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Patent number: 5872904
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 .left brkt-top. log.sub.b N .right brkt-top. stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and .left brkt-top. log.sub.b N .right brkt-top. indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: February 16, 1999
    Assignee: NCR Corporation
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Patent number: 5793937
    Abstract: A method and system which enables the printing of all pages that an interpreter of a page description language can image at the highest print quality that can be maintained while ensuring that all pages will print regardless of complexity. A memory manager is responsible for allocation of memory for rendering pages and a fallback manager is responsible for handling memory overflow and video underrun exceptions.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: August 11, 1998
    Assignee: Peerless Systems Corporation
    Inventors: David J. Chura, Stephen L. Schafer
  • Patent number: 5522046
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 log.sub.b N stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and log.sub.b N indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: May 28, 1996
    Assignee: NCR Corporation
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Patent number: 5321813
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 log.sub.b N stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and log.sub.b N indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: May 1, 1991
    Date of Patent: June 14, 1994
    Assignee: Teradata Corporation
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Patent number: 5303383
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 log.sub.b N stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and log.sub.b N indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: August 14, 1992
    Date of Patent: April 12, 1994
    Assignee: NCR Corporation
    Inventors: Philip M. Neches, Robert J. McMillen, M. Cameron Watson, David J. Chura