Patents by Inventor David J. Comer
David J. Comer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7020675Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistors groups, each of the transistor groups has a plurality of binary weighted transistor pairs. A select unit selects the binary weighted transistor pairs based on binary code signals so that each transistor pair passes a current from one of the source nodes to either a reference node or a summing node.Type: GrantFiled: March 26, 2002Date of Patent: March 28, 2006Assignee: Intel CorporationInventors: David J. Comer, Aaron K. Martin, James E. Jaussi
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Patent number: 7010563Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistor groups, each of the transistor groups includes a plurality of transistor pairs. The values of currents produced by the output stage can be controlled by selecting appropriate parameters of the transistor pairs.Type: GrantFiled: March 26, 2002Date of Patent: March 7, 2006Assignee: Intel CorporationInventors: David J. Comer, Aaron K. Martin, James E. Jaussi
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Patent number: 6856198Abstract: An amplifier includes a differential unit including an input port to receive a voltage input signal, a current mirror unit including an output port, and a voltage-to-current conversion unit to couple the differential unit to the current mirror unit and to generate a current signal to drive the current mirror unit to generate a current output signal at the output port. A method includes receiving a voltage input signal at an input port of a differential unit, converting the voltage input signal to a current signal, and driving a current mirror with the current signal to generate an current output signal at an output port.Type: GrantFiled: December 23, 2002Date of Patent: February 15, 2005Assignee: Intel CorporationInventors: James E. Jaussi, David J. Comer
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Patent number: 6784737Abstract: A voltage multiplier circuit includes a voltage-to-current converter, a current multiplier, and load devices. The voltage-to-current converter receives a differential input voltage, and produces a differential current. The differential current is received by the current multiplier, which produces a scaled output current. The amount of scaling is provided by a digital control word. Load devices produce a differential output voltage from the scaled output current. Multiple voltage-to-current converters and current multipliers can be coupled in parallel so that the scaled output currents sum.Type: GrantFiled: December 17, 2001Date of Patent: August 31, 2004Assignee: Intel CorporationInventors: Aaron K. Martin, David J. Comer
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Publication number: 20040125879Abstract: An information transmission unit includes a signal source, a channel having a channel cutoff frequency coupled to the signal source, a continuous-time linear active filter coupled to the channel to provide equalization over a range of frequencies, and a sampling unit coupled to the continuous-time linear active filter. A method includes transmitting a continuous time signal including digital information on a channel, receiving the continuous time signal from the channel and filtering the continuous time signal to form an equalized continuous time signal, and sampling the equalized continuous time signal to recover the digital information.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: James E. Jaussi, Bryan K. Casper, David J. Comer
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Publication number: 20040119537Abstract: An amplifier includes a differential unit including an input port to receive a voltage input signal, a current mirror unit including an output port, and a voltage-to-current conversion unit to couple the differential unit to the current mirror unit and to generate a current signal to drive the current mirror unit to generate a current output signal at the output port. A method includes receiving a voltage input signal at an input port of a differential unit, converting the voltage input signal to a current signal, and driving a current mirror with the current signal to generate an current output signal at an output port.Type: ApplicationFiled: December 23, 2002Publication date: June 24, 2004Inventors: James E. Jaussi, David J. Comer
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Patent number: 6630818Abstract: A current mirror includes an input node to receive an input current, an output node to produce an output current, and a reference node. The current mirror also includes a potential reduction unit to allow the voltage at the input node to be less than the voltage at the reference node.Type: GrantFiled: March 26, 2002Date of Patent: October 7, 2003Assignee: Intel CorporationInventors: David J. Comer, Aaron K. Martin, James E. Jaussi
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Publication number: 20030184274Abstract: A current mirror includes an input node to receive an input current, an output node to produce an output current, and a reference node. The current mirror also includes a potential reduction unit to allow the voltage at the input node to be less than the voltage at the reference node.Type: ApplicationFiled: March 26, 2002Publication date: October 2, 2003Applicant: Intel CorporationInventors: David J. Comer, Aaron K. Martin, James E. Jaussi
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Publication number: 20030184338Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistor groups, each of the transistor groups includes a plurality of transistor pairs. The values of currents produced by the output stage can be controlled by selecting appropriate parameters of the transistor pairs.Type: ApplicationFiled: March 26, 2002Publication date: October 2, 2003Applicant: Intel CorporationInventors: David J. Comer, Aaron K. Martin, James E. Jaussi
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Publication number: 20030187903Abstract: A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistors groups, each of the transistor groups has a plurality of binary weighted transistor pairs. A select unit selects the binary weighted transistor pairs based on binary code signals so that each transistor pair passes a current from one of the source nodes to either a reference node or a summing node.Type: ApplicationFiled: March 26, 2002Publication date: October 2, 2003Applicant: Intel CorporationInventors: David J. Comer, Aaron K. Martin, James E. Jaussi
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Publication number: 20030112644Abstract: A voltage multiplier circuit includes a voltage-to-current converter, a current multiplier, and load devices. The voltage-to-current converter receives a differential input voltage, and produces a differential current. The differential current is received by the current multiplier, which produces a scaled output current. The amount of scaling is provided by a digital control word. Load devices produce a differential output voltage from the scaled output current. Multiple voltage-to-current converters and current multipliers can be coupled in parallel so that the scaled output currents sum.Type: ApplicationFiled: December 17, 2001Publication date: June 19, 2003Applicant: Intel CorporationInventors: Aaron K. Martin, David J. Comer
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Patent number: 6563369Abstract: A current summing circuit includes an active cascode pair of transistors having a source-drain junction connected to a summing node to receive an input current at the source-drain junction to output an output current at a source of a transistor of the active cascode pair of transistors.Type: GrantFiled: March 26, 2002Date of Patent: May 13, 2003Assignee: Intel CorporationInventors: David J. Comer, Aaron K. Martin, James E. Jaussi