Abstract: A zero turning radius mower park brake system includes a park brake pawl on a transmission which engages a park brake to a pair of independently driven traction wheels. A park brake link may be pivotably mounted to the park brake pawl and connected to a left steering lever and a right steering lever. The park brake link may pivot while moving the park brake pawl forward to a park brake engaged position if only one of the steering levers is moved outward from a neutral traction drive position.

Abstract: Technical solutions are described herein for fabrication of a chip with optimized chip design during the logical synthesis phase of the fabrication. An example method includes optimizing, by a physical synthesis system, a chip design for a chip to be fabricated, the optimization performed according to a first performance metric for the entire chip. The method further includes receiving, by the physical synthesis system, a feedback input comprising a region of the chip and a second performance metric associated with the region. The method further includes modifying, by the physical synthesis system, the chip design by optimizing the region of the chip according to the second performance metric. The method further includes sending, by the physical synthesis system, the modified chip design for fabrication of the chip.

Abstract: Technical solutions are described herein for fabrication of a chip with optimized chip design during the logical synthesis phase of the fabrication. An example method includes optimizing, by a physical synthesis system, a chip design for a chip to be fabricated, the optimization performed according to a first performance metric for the entire chip. The method further includes receiving, by the physical synthesis system, a feedback input comprising a region of the chip and a second performance metric associated with the region. The method further includes modifying, by the physical synthesis system, the chip design by optimizing the region of the chip according to the second performance metric. The method further includes sending, by the physical synthesis system, the modified chip design for fabrication of the chip.

Abstract: Techniques for transforming input operands to reduce overhead for implementing addition operations in hardware are provided. In one aspect, a method for transforming input operands of an adder includes the steps of: receiving a bit array of the input operands; replacing a duplicate signal (e.g., a signal that occurs twice) for a given bit k in the bit array with a single signal at bit k+1; reducing a number of occurrences of the signal on adjacent bits of the input operand, wherein by way of the replacing and reducing a transformed bit array is formed; and providing the transformed bit array to the adder.

Abstract: Techniques for transforming input operands to reduce overhead for implementing addition operations in hardware are provided. In one aspect, a method for transforming input operands of an adder includes the steps of: receiving a bit array of the input operands; replacing a duplicate signal (e.g., a signal that occurs twice) for a given bit k in the bit array with a single signal at bit k+1; reducing a number of occurrences of the signal on adjacent bits of the input operand, wherein by way of the replacing and reducing a transformed bit array is formed; and providing the transformed bit array to the adder.

Abstract: A method, system and computer program product for forming a netlist for an electronic circuit is disclosed. A Very High Speed Integrated Circuit Hardware Description Language (VHDL) file is created for a plurality of voltage domains. The VHDL file includes a voltage domain attribute and a logic voltage attribute for a pin of the electronic circuit. The voltage domain attribute and the logic voltage attribute for the pin are read from the VHDL file. Netlist instructions for the pin are synthesized to form a netlist for the electronic circuit. Synthesizing the netlist instructions begins with synthesizing netlist instructions within a voltage domain indicated by the voltage domain attribute and ends with synthesizing netlist instructions within a voltage domain indicated by the logic voltage attribute.

Abstract: A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other. Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages.

Abstract: A method, computer program product, and data processing system for efficiently performing automated placement of timing-critical unit-level cells in a hierarchical integrated circuit design is disclosed. In preparation for global optimization the entire unit at the cell level, macro-level cells are assigned a “placement force” that serves to limit the movement of the macro-level cells from their current position. Movement boundaries for each macro element are also defined, so as to keep the components in a given macro element in relative proximity to each other. Optimization/placement of the unit design is then performed, via a force-directed layout algorithm, on a “flattened” model of the design while respecting the movement boundaries. Following this “flattened” optimization, the placed “unit-level” cells are modeled as blockages and the macro elements are optimized individually, while respecting the location(s) of the blockages.

Abstract: A reticle assembly, exposure system, and method for exposing each of a plurality of levels of a single die or device dies of a semiconductor wafer to a pattern of radiation on a site-by-site exposure basis are disclosed. Radiation patterning means between a source of radiation and the semiconductor wafer pattern the radiation onto the semiconductor wafer and a stepping means incrementally moves the semiconductor wafer relative to the patterning means for exposing the device dies, one at a time, in succession. The patterning means includes a reticle assembly having a plurality of reticles arranged in a coplanar array with each reticle having a respective different die exposure pattern.