Patents by Inventor David J. Harriman

David J. Harriman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10884965
    Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: January 5, 2021
    Assignee: INTEL CORPORATION
    Inventors: David J. Harriman, Maxim Dan
  • Patent number: 10877915
    Abstract: A flattening portal bridge (FPB) is provided to support addressing according to a first addressing scheme and a second, alternative addressing scheme. The FPB comprises a primary side and a secondary side, the primary side connects to a first set of devices addressed according to a first addressing scheme, and the secondary side connects to a second set of devices addressed according to a second addressing scheme. The first addressing scheme uses a unique bus number within a Bus/Device/Function (BDF) address space for each device in the first set of devices, and the second bus addressing scheme uses a unique bus-device number for each device in the second set of devices.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: David J. Harriman, Reuven Rozic, Maxim Dan, Prashant Sethi, Robert E. Gough, Shanthanand Kutuva Rabindranath
  • Publication number: 20200328879
    Abstract: An apparatus includes a port with circuitry to implement one or more layers of a Compute Express Link (CXL)-based protocol. The port includes an agent to obtain information to be transmitted to another device over a link based on the CXL-based protocol via a flit, encrypt at least a portion of the information to yield a ciphertext, generate a cyclic redundancy check (CRC) code based on the ciphertext, and cause a flit to be generated comprising the ciphertext. The port is to use the circuitry to transmit the flit and the CRC code to the other device over the link.
    Type: Application
    Filed: June 23, 2020
    Publication date: October 15, 2020
    Applicant: Intel Corporation
    Inventors: Raghunandan Makaram, Ishwar Agarwal, Kirk S. Yap, Nitish Paliwal, David J. Harriman, Ioannis T. Schoinas
  • Publication number: 20200319898
    Abstract: Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.
    Type: Application
    Filed: January 27, 2020
    Publication date: October 8, 2020
    Applicant: Intel Corporation
    Inventors: Vinay Raghav, Reuven Rozic, David J. Harriman
  • Publication number: 20200278733
    Abstract: An interface of a device is used to couple to another device and includes a set of data pins to support high speed data communication on an interconnect link between the devices based on an interconnect protocol. The interface further includes at least one auxiliary pin to support a particular signal defined by the interconnect protocol. The device is further configurated to generate hint data for use by the other device and send the hint data as a sideband signal to the other device over the auxiliary pin, where the sideband signal is distinct from signals defined for the auxiliary pin by the interconnect protocol.
    Type: Application
    Filed: May 15, 2020
    Publication date: September 3, 2020
    Applicant: Intel Corporation
    Inventors: Ang Li, David J. Harriman, Kuan Hua Tan
  • Patent number: 10754808
    Abstract: Bridge logic is provided to receive a request from a device, where the request references an address of a secondary address space. The secondary address space corresponds to a subset of addresses in a configuration address space of a system, and the secondary address space corresponds to a first view of the configuration address space. The bridge logic uses a mapping table to translate the address into a corresponding address in the configuration address space, where addresses of the configuration address space correspond to a different second view of the configuration address space.
    Type: Grant
    Filed: December 20, 2015
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Prashant Sethi, Michael T. Klinglesmith, David J. Harriman, Reuven Rozic, Shanthanand Kutuva Rabindrananth
  • Publication number: 20200226091
    Abstract: A device includes protocol logic to determine a packet type for a packet and generate and send the corresponding packet. The packet includes a packet header with a header base, the header base including a type field and a header content field. The type field indicates the packet type and the header content field indicates which of a plurality of header content blocks is to be included in the packet header with the header base. Information in fields of the header base indicate a total length of the packet.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventor: David J. Harriman
  • Publication number: 20200210363
    Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.
    Type: Application
    Filed: December 26, 2019
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Vinay Raghav, David J. Harriman, Utkarsh Y. Kakaiya
  • Publication number: 20200151362
    Abstract: A system may include a root port and an endpoint upstream port. The root port may include transaction layer hardware circuitry to determine, by logic circuitry at a transaction layer of a protocol stack of a device, that a packet is to traverse to a link partner on a secure stream, authenticate a receiving port of the link partner, configure a transaction layer packet (TLP) prefix to identify the TLP as a secure TLP, associating the secure TLP with the secure stream, apply integrity protection and data encryption to the Secure TLP, transmit the secure TLP across the secure stream to the link partner.
    Type: Application
    Filed: January 10, 2020
    Publication date: May 14, 2020
    Applicant: Intel Corporation
    Inventors: David J. Harriman, Raghunandan Makaram, Ioannis T. Schoinas, Vedvyas Shanbhogue, Siddhartha Chhabra, Kapil Sood
  • Publication number: 20200110725
    Abstract: A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages.
    Type: Application
    Filed: July 22, 2019
    Publication date: April 9, 2020
    Applicant: Intel Corporation
    Inventors: David J. Harriman, Jasmin Ajanovic
  • Publication number: 20200042482
    Abstract: Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed.
    Type: Application
    Filed: August 19, 2019
    Publication date: February 6, 2020
    Inventors: David J. Harriman, Maxim Dan
  • Patent number: 10545773
    Abstract: Aspects of the embodiments include systems, methods, devices, and computer program products to receive, from the downstream component, an indication of an extended capability; determining, from the indication, one or more configuration parameters for the downstream component; applying the one or more configuration parameters; and performing data signal or control signal transmissions across the PCIe-compliant link with the downstream component based, at least in part, on the applied one or more configuration parameters. The extended capabilities can be indicated by a DVSEC extended capability definition received from a downstream device. The extended capabilities of the downstream component can indicate the number of buses, the port type, the expandability capability, the D3Cold support status, the host router indicator, and/or the safe eject requirements of the downstream component.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Vinay Raghav, Reuven Rozic, David J. Harriman
  • Publication number: 20200019522
    Abstract: A data structure is accessed that defines configuration parameters of one or more integrated blocks in an integrated circuit device. One or more of the integrated blocks is configured based on corresponding configuration parameters defined in the data structure. The configuration parameters are set prior to runtime and are to be persistently stored in the data structure.
    Type: Application
    Filed: September 23, 2019
    Publication date: January 16, 2020
    Applicant: Intel Corporation
    Inventor: David J. Harriman
  • Publication number: 20200004703
    Abstract: Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.
    Type: Application
    Filed: September 10, 2019
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Rajesh M. Sankaran, David J. Harriman, Sean O. Stalley, Rupin H. Vakharwala, Ishwar Agarwal, Pratik M. Marolia, Stephen R. Van Doren
  • Patent number: 10521388
    Abstract: A device includes a plurality of ports and a plurality of capability registers that correspond to a respective one of the plurality of ports. The device is to connect to one or more processors of a host device through the plurality of ports, and each of the plurality of ports comprises a respective protocol stack to support a respective link between the corresponding port and the host device according to a particular interconnect protocol. Each of the plurality of capability registers comprises a respective set of fields for use in configuration of the link between its corresponding port and one of the one or more processors of the host device. The fields include a field to indicate an association between the port and a particular processor, a field to indicate a port identifier for the port, and a field to indicate a total number of ports of the device.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Vinay Raghav, David J. Harriman, Utkarsh Y. Kakaiya
  • Patent number: 10509729
    Abstract: Embodiments of an invention for address translation for scalable I/O device virtualization are disclosed. In one embodiment, an apparatus includes PASID table lookup circuitry. The PASID table lookup circuitry is to find a PASID-entry in a PASID table. The PASID-entry is to include a PASID processing mode (PPM) indicator and a first pointer to a first translation structure. The PPM indicator is to specify one of a plurality of translation types, the one of the plurality of translation types to use the first translation structure.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: December 17, 2019
    Assignee: Intel Corporation
    Inventors: Rajesh M Sankaran, Randolph L Campbell, Prashant Sethi, David J Harriman
  • Publication number: 20190324523
    Abstract: A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.
    Type: Application
    Filed: June 29, 2019
    Publication date: October 24, 2019
    Inventors: Michelle C. Jen, David J. Harriman, Zuoguo Wu, Debendra Das Sharma, Noam Dolev Geldbard
  • Publication number: 20190306134
    Abstract: Methods, systems, and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed. An apparatus comprises a first device comprising circuitry to, using an end-to-end protocol, secure a transaction in a first secure stream based at least in part on a transaction type of the transaction, where the first secure stream is separate from a second secure stream. The first device is further to send the transaction secured in the first secure stream to a second device over a link established between the first device and the second device, where the transaction is to traverse one or more intermediate devices from the first device to the second device. In more specific embodiments, the first secure stream is based on one of a posted transaction type, a non-posted transaction type, or completion transaction type.
    Type: Application
    Filed: June 18, 2019
    Publication date: October 3, 2019
    Applicant: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Siddhartha Chhabra, David J. Harriman, Raghunandan Makaram, Ioannis T. Schoinas
  • Patent number: 10423552
    Abstract: A data structure is accessed that defines configuration parameters of one or more integrated blocks in an integrated circuit device. One or more of the integrated blocks is configured based on corresponding configuration parameters defined in the data structure. The configuration parameters are set prior to runtime and are to be persistently stored in the data structure.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventor: David J. Harriman
  • Publication number: 20190286605
    Abstract: A port of a computing device includes protocol circuitry to implement a particular interconnect protocol, where the protocol circuitry is to generate a set of ordered sets defined according to the particular interconnect protocol. The set of ordered sets is generated for a link to couple a first device to a second device and the set of ordered sets comprises link information for the link. Translation layer circuitry is provided to: generate, from the set of ordered sets, at least one data structure to comprise at least a portion of the link information, and cause the data structure to be sent from the first device to the second device on the link in lieu of the set of ordered sets.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Applicant: Intel Corporation
    Inventor: David J. Harriman