Patents by Inventor David J. Hill

David J. Hill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190278746
    Abstract: Systems, methods, and non-transitory computer readable media for storing and processing metadata corresponding to files are presented. The system comprises first, second, and third computing nodes. The computing nodes comprise a plurality of slices of a metadata database that is separate and independent from file storage, and each slice is configured to store metadata. The computing nodes further comprise a slice route table that indicates primary and secondary locations of each unique slice in the plurality of slices. The slice route table comprises a plurality of entries, each of which comprise a slice number corresponding to a slice in the plurality of slices of the metadata database, a primary computing node number corresponding to a primary computing node that comprises the slice and corresponds to the primary location, and a secondary computing node number corresponding to a secondary computing node that comprises the slice and corresponds to the secondary location.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 12, 2019
    Inventors: Mark U. Cree, James M. Rolette, Jason D. Preston, Matthew C. Laswell, Chris J. Richards, David A. Yoakley, Russell S. Hill
  • Patent number: 10407985
    Abstract: A bracket assembly that secures cables to rungs of a ladder rack. The bracket has a bottom portion, sidewalls, and an upper portion. The bracket is positioned under the rectangular body of the ladder rung and secured thereto with an interference fit. At least one cable is positioned on the ladder rung and the upper portion of the bracket. A tie secures the cable to the upper portion of the bracket.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: September 10, 2019
    Assignee: Panduit Corp.
    Inventors: David J. Sylvester, Rodney G. Rouleau, Raymond M. Hill, Andrew Crouse, Janina B. Nebes
  • Publication number: 20190267396
    Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Applicant: Micron Technology, Inc.
    Inventors: David Daycock, Richard J. Hill, Christopher Larsen, Woohee Kim, Justin B. Dorhout, Brett D. Lowe, John D. Hopkins, Qian Tao, Barbara L. Casey
  • Publication number: 20190216550
    Abstract: A robotic surgical system can include one or more adjustable arm supports that support one or more robotic arms. The adjustable arm supports and/or robotic arms can be configured to be deployed from low mount positions, for example, from positions below the surface of the table. The robotic arms can include a plurality of joints providing a plurality of degrees of freedom. The joints may be grouped into a proximal shoulder, an elbow, and a distal wrist. The robotic arms can include one or more redundant degrees of freedom. An insertion mechanism, associated with the robotic arm and configured for providing insertion of an instrument along an assertion axis, can be provided at a distal end of the robotic arms.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 18, 2019
    Inventors: Nicholas J. Eyre, Aren Calder Hill, Sven Wehrmann, Colin Allen Wilson, Yanan Huang, Jason Tomas Wilson, David Stephen Mintz
  • Patent number: 10335280
    Abstract: A method for treating a human patient includes emitting ultrasound energy from an ultrasound transducer positioned remotely from target tissue of the patient. The ultrasound transducer is positioned at a desired location relative to the patient and target tissue using location and imaging techniques. The method further includes focusing the ultrasound energy such that one or more focal points are directed to the target tissue of the patient and ablating the target tissue at each focal point. The target tissue is ablated via the focused ultrasound energy without ablating non-target tissue through which the ultrasound energy passes between the ultrasound transducer and the one or more focal points.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: July 2, 2019
    Assignee: Medtronic, Inc.
    Inventors: James R. Keogh, Timothy R. Ryan, Carol E. Eberhardt, Mark T. Stewart, James R. Skarda, Timothy G. Laske, Alexander J. Hill, Jack D. Lemmon, David E. Francischelli
  • Publication number: 20190189515
    Abstract: An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 20, 2019
    Inventors: David K. Hwang, John A. Smythe, Haitao Liu, Richard J. Hill, Deepak Chandra Pandey
  • Patent number: 10314700
    Abstract: A composite biomaterial having a continuous metal sheet with arcuate members that define a first fenestration pattern, and a polymer layer over at least one surface of the continuous metal sheet. The arcuate members elastically stretch to allow the continuous metal sheet to bend in more than one axis without buckling or wrinkling.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: June 11, 2019
    Assignee: Boston Scientific Scimed, Inc.
    Inventors: David J. Sogard, Scott R. Smith, Jason P. Hill, Patrick A. Haverkost, Susan M. Shoemaker
  • Patent number: 10316338
    Abstract: Disclosed are methods of synthesizing enantioenriched difluoroalkylcyclopropyl amino esters and their salts, such as the dicyclohexylamine salt of (1S,2R)-2-(difluoromethyl)-1-(propoxycarbonyl)cyclopropane carboxylic acid. These compounds are useful intermediates in the synthesis of viral protease inhibitors.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: June 11, 2019
    Assignee: Abb Vie Inc.
    Inventors: Michael J. Abrahamson, Angelica B. Kielbus, William T. Riordan, David R. Hill, Sanjay R. Chemburkar, Rajarathnam E. Reddy, Timothy B. Towne, Jianzhang Mei, Gareth J. Brown, Stefan Mix
  • Patent number: 10304853
    Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David Daycock, Richard J. Hill, Christopher Larsen, Woohee Kim, Justin B. Dorhout, Brett D. Lowe, John D. Hopkins, Qian Tao, Barbara L. Casey
  • Publication number: 20190002150
    Abstract: This disclosure provides methods, systems and devices that may be used to measure, calculate, and orient a device such as a drill bit in a downhole environment. To that end, disclosed are fiber optic gyroscopes, wherein the fiber optic gyroscopes comprise elliptical fiber optic cable coils in a mutually orthogonal arrangement that is tilted relative to a length of a supporting shaft, e.g., tube. Light travels in opposite directions within each of the elliptical fiber optic cable coils, and, subsequently, sensors detect differences in time for each light path of the light that traveled in opposite directions within each one of the elliptical fiber optic cable coils. The elliptical nature of the fiber optic cable coils minimizes the cross-sectional area of the mutually orthogonal arrangement, and thereby makes it well-suited for use in downhole environments where space is at a premium. This disclosure also may provide an inertial measurement unit.
    Type: Application
    Filed: September 10, 2018
    Publication date: January 3, 2019
    Applicant: Jindal Films Americas LLC
    Inventors: Daniel L. Hinman, Mark W. Lockhart, Terry O. Jensen, Robert M. Sheppard, Thierry J. L. Dabadie, Alexandra N. Wolfe, Anand Sundararaman, David J. Hill, David Piran
  • Patent number: 9711422
    Abstract: Methods and structures provide an electrostatic discharge (ESD) indicator including an electric field sensitive material configured to undergo a specific color change in response to an electric field. An exposure of the structure to an ESD can be visually determined via the specific color change of the ESD indicator.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: July 18, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Stephen P. Ayotte, David J. Hill, John T. Kinnear, Jr., Glen E. Richard, Timothy M. Sullivan, Heather M. Truax
  • Publication number: 20150355253
    Abstract: Methods and structures provide an electrostatic discharge (ESD) indicator including an electric field sensitive material configured to undergo a specific color change in response to an electric field. An exposure of the structure to an ESD can be visually determined via the specific color change of the ESD indicator.
    Type: Application
    Filed: August 7, 2015
    Publication date: December 10, 2015
    Inventors: Stephen P. Ayotte, David J. Hill, John T. Kinnear, JR., Glen E. Richard, Timothy M. Sullivan, Heather M. Truax
  • Patent number: 9105573
    Abstract: Methods and structures provide an electrostatic discharge (ESD) indicator including an electric field sensitive material configured to undergo a specific color change in response to an electric field. An exposure of the structure to an ESD can be visually determined via the specific color change of the ESD indicator.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stephen P. Ayotte, David J. Hill, John T. Kinnear, Jr., Glen E. Richard, Timothy M. Sullivan, Heather M. Truax
  • Patent number: 9059097
    Abstract: Aspects of the disclosure provide a method of inhibiting crack propagation in a silicon wafer. In one embodiment, a method of repairing an imperfection on a surface of a semiconductor device is disclosed. The method includes: screening for imperfections on a surface of a silicon wafer of a semiconductor device; and in response to at least one imperfection on the surface of the silicon wafer, depositing a material on the surface of the silicon wafer.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stephen P. Ayotte, David J. Hill, Glen E. Richard, Timothy M. Sullivan, Heather M. Truax
  • Patent number: 8829674
    Abstract: Stacked multichip packages and methods of making multichip packages. A method includes using a boat having different depth openings corresponding to the length of column interconnections of the completed multichip package and masks to place proper length columns in the corresponding depth openings; placing an integrated circuit chip on the boat and attaching exposed upper ends of the columns to respective chip pads of the integrated circuit using a first solder reflow process and attaching a preformed package substrate integrated circuit chip stack to the integrated circuit and attached columns using a second solder reflow process.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen P. Ayotte, David J. Hill, Timothy M. Sullivan
  • Publication number: 20140183723
    Abstract: Stacked multichip packages and methods of making multichip packages. A method includes using a boat having different depth openings corresponding to the length of column interconnections of the completed multichip package and masks to place proper length columns in the corresponding depth openings; placing an integrated circuit chip on the boat and attaching exposed upper ends of the columns to respective chip pads of the integrated circuit using a first solder reflow process and attaching a preformed package substrate integrated circuit chip stack to the integrated circuit and attached columns using a second solder reflow process.
    Type: Application
    Filed: January 2, 2013
    Publication date: July 3, 2014
    Applicant: International Business Machines Corporation
    Inventors: Stephen P. Ayotte, David J. Hill, Timothy M. Sullivan
  • Patent number: 8765593
    Abstract: Aspects of the present invention relate to a controlled collapse chip connection (C4) structures. Various embodiments include a method of forming a controlled collapse chip connection (C4) structure. The method can include: providing a precursor structure including: a substrate, a dielectric over the substrate, the dielectric including a plurality of trenches exposing a portion of the substrate, and a metal layer over the dielectric and the portion of the substrate in each of the plurality of trenches, forming a resist layer over the metal layer, forming a rigid liner over a surface of the resist layer and the metal layer, and forming solder over the rigid liner between portions of the resist layer.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen P. Ayotte, Timothy H. Daubenspeck, David J. Hill, Glen E. Richard, Timothy M. Sullivan
  • Publication number: 20140042630
    Abstract: Aspects of the present invention relate to a controlled collapse chip connection (C4) structures. Various embodiments include a method of forming a controlled collapse chip connection (C4) structure. The method can include: providing a precursor structure including: a substrate, a dielectric over the substrate, the dielectric including a plurality of trenches exposing a portion of the substrate, and a metal layer over the dielectric and the portion of the substrate in each of the plurality of trenches, forming a resist layer over the metal layer, forming a rigid liner over a surface of the resist layer and the metal layer, and forming solder over the rigid liner between portions of the resist layer.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen P. Ayotte, Timothy H. Daubenspeck, David J. Hill, Glen E. Richard, Timothy M. Sullivan
  • Publication number: 20140042594
    Abstract: Aspects of the disclosure provide a method of inhibiting crack propagation in a silicon wafer. In one embodiment, a method of repairing an imperfection on a surface of a semiconductor device is disclosed. The method includes: screening for imperfections on a surface of a silicon wafer of a semiconductor device; and in response to at least one imperfection on the surface of the silicon wafer, depositing a material on the surface of the silicon wafer.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen P. Ayotte, David J. Hill, Glen E. Richard, Timothy M. Sullivan, Heather M. Truax
  • Publication number: 20130257624
    Abstract: Methods and structures provide an electrostatic discharge (ESD) indicator including an electric field sensitive material configured to undergo a specific color change in response to an electric field. An exposure of the structure to an ESD can be visually determined via the specific color change of the ESD indicator.
    Type: Application
    Filed: March 28, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen P. AYOTTE, David J. HILL, John T. KINNEAR, JR., Glen E. RICHARD, Timothy M. SULLIVAN, Heather M. TRUAX