Abstract: The present invention is directed to an improved PLL which produces an output signal that is in-phase with a reference clock input despite switching of the reference clock. A quadrature signal is generated using a quadrature decoder having a counter, a state decoder and a flip flop. A local oscillator having a local clock output having a frequency which is a multiple of the reference clock frequency is provided. The local clock output is divided down with a binary counter to match the reference signal frequency. The counter state is decoded using an AND in combination with a flip flop. The divided clock output is then re-synchronized with the reference clock using the local clock output coupled to the clock input of the flip flop. The output of the flip flop is an quadrature copy of the reference clock, and this quadrature signal is fed back to the phase detector.