Patents by Inventor David J. Kachmarik

David J. Kachmarik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8072308
    Abstract: A high voltage split core transformer and method of assembling same is provided by which the coupling factor is improved. A split core assembly is surrounded by a secondary winding that is precisely located in a burner assembly housing. Conductive members are encased within the housing and, in conjunction with traces provided on a printed circuit board enclosing the housing cavity, define first and second primary windings about the core secondary winding. This arrangement reduces the number of turns in the secondary winding and allows the use of larger cross-sectional wire which increases the current carrying capability thereof, making the transformer suitable for D1-D5 automotive headlamp applications.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: December 6, 2011
    Assignee: General Electric Company
    Inventors: Tony Aboumrad, David J Kachmarik
  • Patent number: 7772780
    Abstract: Disclosed are a lamp igniter module and method of assembling a lamp igniter module. The lamp igniter module comprises a transformer carrier, a slide-in electrical connector, a pc board, and a housing. Assembly of the lamp igniter module is accomplished by initially inserting a transformer carrier assembly within the housing and subsequently installing a slide-in electrical connector which may or may not be attached to the pc board.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: August 10, 2010
    Assignee: General Electric Company
    Inventors: Rajendra K. Pokharna, David J. Kachmarik, Virgil Chichernea, Bruce Roberts, David A. D'Onofrio
  • Publication number: 20080204180
    Abstract: A high voltage split core transformer and method of assembling same is provided by which the coupling factor is improved. A split core assembly is surrounded by a secondary winding that is precisely located in a burner assembly housing. Conductive members are encased within the housing and, in conjunction with traces provided on a printed circuit board enclosing the housing cavity, define first and second primary windings about the core secondary winding. This arrangement reduces the number of turns in the secondary winding and allows the use of larger cross-sectional wire which increases the current carrying capability thereof, making the transformer suitable for D1-D5 automotive headlamp applications.
    Type: Application
    Filed: February 26, 2007
    Publication date: August 28, 2008
    Inventors: Tony Aboumrad, David J. Kachmarik
  • Publication number: 20080157696
    Abstract: Disclosed are a lamp igniter module and method of assembling a lamp igniter module. The lamp igniter module comprises a transformer carrier, a slide-in electrical connector, a pc board, and a housing. Assembly of the lamp igniter module is accomplished by initially inserting a transformer carrier assembly within the housing and subsequently installing a slide-in electrical connector which may or may not be attached to the pc board.
    Type: Application
    Filed: December 27, 2006
    Publication date: July 3, 2008
    Inventors: Rajendra K. Pokharna, David J. Kachmarik, Virgil Chichernea, Bruce Roberts, David A. D'Onofrio
  • Patent number: 7102298
    Abstract: An integrated lamp/lamp electronics unit includes a lamp having a first end with first end electrical terminals, and a second end with second end electrical terminals. An end cap having an interior section is placed into electrical connection with the first end electrical terminals at the first end of the lamp. Lamp electronics are configured to control operation of the lamp and are connected only to the second end electrical terminals. The lamp electronics are carried on a circuit board having a configuration substantially matching the second end of the lamp portion. The circuit board is placed within the interior of a lamp electronics end cap, and the end cap is attached in a permanent relationship to the second end of the lamp.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: September 5, 2006
    Assignee: General Electric Company
    Inventors: Louis R. Nerone, David J. Kachmarik, Joseph C. Oberle, Michael S. Idelchik
  • Patent number: 6756746
    Abstract: An inverter circuit for ballasting a gas discharge lamp having a delay circuit designed to delay regenerative control of the inverter switches until a d.c. bus has attained steady-state operating d.c. voltage. The inverter circuit includes a drive control circuit for inducing an a.c. load current. The inverter circuit includes first and second complementary switches serially connected between the bus and a reference bus. The switches are connected together at a common node through which the a.c. load current flows. A driving inductor is connected at one end to the common node and operatively connected at the remaining end to a control node. A load circuit includes a resonant inductor connected at one end to the common node, with the resonant inductor mutually coupled to the driving inductor. A resonant capacitor is serially connected between the remaining end of the resonant inductor and the reference bus. The gas discharge lamp is serially connected with a d.c.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: June 29, 2004
    Assignee: General Electric Company
    Inventors: Louis R. Nerone, David J. Kachmarik, Melvin C. Cosby, Jr.
  • Patent number: 6686705
    Abstract: A ballast circuit is provided, comprising: a plurality of inverters, each inverter for powering a load; and a controller operationally coupled to a shutdown control signal of each inverter for selectively shutting down any combination of inverters. In another aspect, the controller is for selectively disabling any combination of inverters to effectively disconnect the load associated with each disabled inverter. The controller is for receiving communications from a control device, each communication a selection of 0%, “n−1” approximate percentages each associated with a ratio of “1” through “n−1” loads to “n” loads, where “n” is the total number of loads powered by the inverters of the ballast circuit and where the numerator for each ratio is an integer between “1” and “n−1,” inclusive, or 100% light from the combined loads powered by the inverters of the ballast circuit.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: February 3, 2004
    Assignee: General Electric Company
    Inventors: Louis R. Nerone, David J. Kachmarik, Melvin C. Cosby
  • Patent number: 6621238
    Abstract: A ballast circuit including a power factor correction circuit with an alterable d.c. bus charging rate is provided. The power factor correction circuit selectively alters the d.c. bus charging rate such that, during a startup period for the ballast circuit, the charging rate is faster than during a steady-state period. The ballast circuit including a bridge rectifier, a power factor correction circuit, a bus capacitor, and at least one inverter. The power factor correction circuit including a power factor controller, a semiconductor switch operationally coupled to an output signal of the power factor controller, a selectively alterable impedance network operationally coupled to an output of the semiconductor switch and operationally coupled to an input signal of the power factor controller, and an impedance network control circuit operationally coupled to the impedance network to selectively alter the impedance network.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: September 16, 2003
    Assignee: General Electric Company
    Inventors: Louis R. Nerone, David J. Kachmarik, Melvin C. Cosby
  • Publication number: 20030141830
    Abstract: A ballast circuit is provided, comprising: a plurality of inverters, each inverter for powering a load; and a controller operationally coupled to a shutdown control signal of each inverter for selectively shutting down any combination of inverters. In another aspect, the controller is for selectively disabling any combination of inverters to effectively disconnect the load associated with each disabled inverter. The controller is for receiving communications from a control device, each communication a selection of 0%, “n−1” approximate percentages each associated with a ratio of “1” through “n−1” loads to “n” loads, where “n” is the total number of loads powered by the inverters of the ballast circuit and where the numerator for each ratio is an integer between “1” and “n−1,” inclusive, or 100% light from the combined loads powered by the inverters of the ballast circuit.
    Type: Application
    Filed: January 25, 2002
    Publication date: July 31, 2003
    Inventors: Louis R. Nerone, David J. Kachmarik, Melvin C. Cosby
  • Publication number: 20030141827
    Abstract: A ballast circuit including a power factor correction circuit with an alterable d.c. bus charging rate is provided. The power factor correction circuit selectively alters the d.c. bus charging rate such that, during a startup period for the ballast circuit, the charging rate is faster than during a steady-state period. The ballast circuit including a bridge rectifier, a power factor correction circuit, a bus capacitor, and at least one inverter. The power factor correction circuit including a power factor controller, a semiconductor switch operationally coupled to an output signal of the power factor controller, a selectively alterable impedance network operationally coupled to an output of the semiconductor switch and operationally coupled to an input signal of the power factor controller, and an impedance network control circuit operationally coupled to the impedance network to selectively alter the impedance network.
    Type: Application
    Filed: January 25, 2002
    Publication date: July 31, 2003
    Inventors: Louis R. Nerone, David J. Kachmarik, Melvin C. Cosby
  • Publication number: 20030094907
    Abstract: An inverter circuit for ballasting a gas discharge lamp having a delay circuit designed to delay regenerative control of the inverter switches until a d.c. bus has attained steady-state operating d.c. voltage. The inverter circuit includes a drive control circuit for inducing an a.c. load current. The inverter circuit includes first and second complementary switches serially connected between the bus and a reference bus. The switches are connected together at a common node through which the a.c. load current flows. A driving inductor is connected at one end to the common node and operatively connected at the remaining end to a control node. A load circuit includes a resonant inductor connected at one end to the common node, with the resonant inductor mutually coupled to the driving inductor. A resonant capacitor is serially connected between the remaining end of the resonant inductor and the reference bus. The gas discharge lamp is serially connected with a d.c.
    Type: Application
    Filed: September 19, 2002
    Publication date: May 22, 2003
    Inventors: Louis R. Nerone, David J. Kachmarik, Melvin C. Cosby
  • Patent number: 6525488
    Abstract: A self-oscillating boost converter includes a resistor-starting network configured to start a charging of the boost converter. A resonant feedback circuit is designed to generate an oscillating signal following the starting of the circuit by the resistor-starting network. A complementary switching network has a pair of complementary common-source connected switches configured to receive the oscillation signal generated by the resonant feedback circuit. The oscillation signal determines a switching rate, or duty cycle, of the complementary pair of switches. A boost inductor is in operational connection with the complementary pair of switches. The switching rate of the complementary switching network acts to determine the boost voltage supplied to a load.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: February 25, 2003
    Assignee: General Electric Company
    Inventors: Louis R. Nerone, David J. Kachmarik
  • Publication number: 20030006718
    Abstract: An integrated lamp/lamp electronics unit includes a lamp having a first end with first end electrical terminals, and a second end with second end electrical terminals. An end cap having an interior section is placed into electrical connection with the first end electrical terminals at the first end of the lamp. Lamp electronics are configured to control operation of the lamp and are connected only to the second end electrical terminals. The lamp electronics are carried on a circuit board having a configuration substantially matching the second end of the lamp portion. The circuit board is placed within the interior of a lamp electronics end cap, and the end cap is attached in a permanent relationship to the second end of the lamp.
    Type: Application
    Filed: August 5, 2002
    Publication date: January 9, 2003
    Inventors: Louis R. Nerone, David J. Kachmarik, Joseph C. Oberle, Michael S. Idelchik
  • Publication number: 20020175638
    Abstract: A self-oscillating boost converter includes a resistor-starting network configured to start a charging of the boost converter. A resonant feedback circuit is designed to generate an oscillating signal following the starting of the circuit by the resistor-starting network. A complementary switching network has a pair of complementary common-source connected switches configured to receive the oscillation signal generated by the resonant feedback circuit. The oscillation signal determines a switching rate, or duty cycle, of the complementary pair of switches. A boost inductor is in operational connection with the complementary pair of switches. The switching rate of the complementary switching network acts to determine the boost voltage supplied to a load.
    Type: Application
    Filed: May 18, 2001
    Publication date: November 28, 2002
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Louis R. Nerone, David J. Kachmarik
  • Patent number: 6465972
    Abstract: The present invention provides a lighting system powered by a system power source. The lighting system includes a ballast in operative connection with the system power source where the ballast is designed to generate a lamp input signal. A lamp input line is operatively connected to receive the lamp input signal. Further, a gas discharge lamp is in operative connection to the lamp input line configured to receive the lamp input signal. An amplitude modulation circuit is then placed in operative connection to the lamp input line, where the amplitude modulation circuit is configured to periodically modulate amplitudes of the lamp input signal prior to the lamp input signal being received by the gas discharge lamp. Operation of the amplitude modulation circuit results in a periodic amplitude modulation of the lamp input signal and eliminating visual striations otherwise occurring in the lamp.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: October 15, 2002
    Assignee: General Electric Company
    Inventors: David J. Kachmarik, Louis R. Nerone
  • Patent number: 6459215
    Abstract: An integrated lamp/lamp electronics unit includes a lamp having a first end with first end electrical terminals, and a second end with second end electrical terminals. An end cap having an interior section is placed into electrical connection with the first end electrical terminals at the first end of the lamp. Lamp electronics are configured to control operation of the lamp and are connected only to the second end electrical terminals. The lamp electronics are carried on a circuit board having a configuration substantially matching the second end of the lamp portion. The circuit board is placed within the interior of a lamp electronics end cap, and the end cap is attached in a permanent relationship to the second end of the lamp.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: October 1, 2002
    Assignee: General Electric Company
    Inventors: Louis R. Nerone, David J. Kachmarik, Joseph C. Oberle, Michael S. Idelchik
  • Patent number: 6150769
    Abstract: A ballast circuit for a gas discharge lamp with a tapless feedback circuit is disclosed. The ballast circuit comprises a d.c.-to-a.c. converter circuit with circuitry for coupling to a resonant load circuit, for inducing a.c. current therein. The converter circuit comprises a pair of switches serially connected between a bus conductor at a d.c. voltage and a reference conductor. The voltage between a reference node and a control node of each switch determines the conduction state of the associated switch. The respective reference nodes of the switches are connected together at a common node through which the a.c. current flows, and the respective control nodes of the switches are connected together. A gate drive arrangement regeneratively controls the first and second switches. It comprises a coupling circuit including an inductor for coupling to the control nodes a feedback signal representing current in the load circuit. It further comprises a tapless feedback circuit for providing the feedback signal.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: November 21, 2000
    Assignee: General Electric Company
    Inventors: Louis R. Nerone, David J. Kachmarik
  • Patent number: 6057648
    Abstract: A ballast circuit for a gas discharge lamp includes a d.c.-to-a.c. converter circuit with circuitry for coupling to a load circuit, for inducing a.c. current therein. The converter circuit comprises a pair of switches serially connected between a bus conductor at a d.c. voltage and a reference conductor. The voltage between a reference node and a control node of each switch determines the conduction state of the associated switch. The respective reference nodes of the switches are connected together at a common node through which the a.c. current flows, and the respective control nodes of the switches are connected together. The load circuit has circuitry for connecting to a gas discharge lamp and comprises a piezoelectric transformer having a body and including a reference lead connected to one of the bus and reference conductors, an input lead coupled to the common node, and an output lead connected to the lamp.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: May 2, 2000
    Assignee: General Electric Company
    Inventors: Louis R. Nerone, David J. Kachmarik
  • Patent number: 5917289
    Abstract: A ballast circuit for a gas discharge lamp comprises a resonant load circuit including the lamp. A d.c.-to-a.c. converter circuit induces an a.c. current in the resonant load circuit. The converter circuit comprises first and second switches serially connected between a bus conductor at a d.c. voltage and a reference conductor, and being connected together at a common node through which the a.c. load current flows. The first and second switches each comprise a reference node and a control node, the voltage between such nodes determining the conduction state of the associated switch. The respective reference nodes of the first and second switches are interconnected at the common node. The respective control nodes of the first and second switches are interconnected. An inductance is connected between the control nodes and the common node. A starting pulse-supplying capacitance is connected in series with the inductance, between the control nodes and the common node.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: June 29, 1999
    Assignee: General Electric Company
    Inventors: Louis R. Nerone, David J. Kachmarik, Michael M. Secen
  • Patent number: 5914570
    Abstract: A gas discharge lamp ballast comprises a load circuit including circuitry for connection to a gas discharge lamp. A circuit supplies d.c. power from an a.c. voltage. A d.c.-to-a.c. converter circuit is coupled to the load circuit for inducing a.c. current therein. The converter circuit comprises first and second converter switches serially connected in the foregoing order between a bus node at a d.c. voltage and a reference node, and being connected together at a common node through which the a.c. load current flows. The first and second converter switches each have a control node and a reference node, the voltage between such nodes determining the conduction state of the associated switch. The respective control nodes of the first and second converter switches are interconnected. The respective reference nodes of the first and second converter switches are connected together at the common node.
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: June 22, 1999
    Assignee: General Electric Company
    Inventors: Louis R. Nerone, David J. Kachmarik