Patents by Inventor David J. Katz
David J. Katz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180164969Abstract: A wearable device is described. The wearable device can include a display screen and an outer housing. The outer housing can include a processor, a memory, and a transceiver. The outer housing can be attached to the display screen, and the outer housing can be mounted on an article of clothing. The processor is configured to receive via the transceiver a media from a smart device, and the processor is also configured to cause display of the media on the display screen.Type: ApplicationFiled: December 11, 2017Publication date: June 14, 2018Inventors: David J. KATZ, Jeffrey O. SPIEGEL
-
Patent number: 9390043Abstract: Trigger routing in computational hardware such as a digital-signal processor involves routing a trigger signal from a first, master module to a second, slave module, thereby initiating an event at the slave module without involving a core processing unit.Type: GrantFiled: December 17, 2012Date of Patent: July 12, 2016Assignee: Analog Devices, Inc.Inventors: Richard F. Grafton, John M. Young, David J. Katz
-
Publication number: 20140173147Abstract: Trigger routing in computational hardware such as a digital-signal processor involves routing a trigger signal from a first, master module to a second, slave module, thereby initiating an event at the slave module without involving a core processing unit.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Inventors: Richard F. Grafton, John M. Young, David J. Katz
-
Patent number: 8503593Abstract: In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit configured to provide a feedback signal to a driver IC. The IC system also includes the driver IC configured to receive a second clock signal and includes a waveform generator configured to provide synthesized waveforms from DC to K-band, a serializer/deserializer (SERDES) to receive data from the waveform generator and to provide the signal to the receiver IC and a phase selection circuit to provide a phase selection signal to the first integrated circuit based on the feedback signal. The phase selection signal calibrates the signal from the SERDES and provides phase correction to the SERDES.Type: GrantFiled: June 23, 2010Date of Patent: August 6, 2013Assignee: Raytheon CompanyInventors: David J. Katz, Stephen R. Reid
-
Patent number: 8319523Abstract: In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit to provide a feedback signal to a driver IC. The system also includes the driver IC configured to receive a second clock signal and includes a phase selection circuit configured to provide a phase selection signal to the receiver IC based on the feedback signal. The phase selection signal controls the data received by the receiver IC by adjusting the first clock signal.Type: GrantFiled: June 23, 2010Date of Patent: November 27, 2012Assignee: Raytheon CompanyInventors: Stephen R. Reid, David J. Katz
-
Patent number: 8207021Abstract: An improved microelectronic assembly (100) and packaging method includes a device package for housing a semiconductor die or chip, (105), an array of passive electronic components (305-355) operating in cooperation with the flip chip semiconductor die (105) and housed inside the device package to decouple noise from input signals, and a heat spreader (195) disposed between a top surface of the semiconductor die (105) and a package cover (185). The semiconductor die (105) is configured as a flip chip die and the device package includes a package substrate (110) configured as a ball grid array. The improved microelectronic device (100) reduces parasitic inductance in electrical interconnections between the semiconductor die and an electrical system substrate (115) and reduces signal noise in mixed signal high frequency analog to digital converters operating at clock rates above 1 GHz.Type: GrantFiled: September 23, 2011Date of Patent: June 26, 2012Assignee: Raytheon CompanyInventors: Dennis R. Kling, Bruce William Chignola, David J. Katz, Jorge M. Marcial, Leonard Schaper
-
Publication number: 20120015485Abstract: An improved microelectronic assembly (100) and packaging method includes a device package for housing a semiconductor die or chip, (105), an array of passive electronic components (305-355) operating in cooperation with the flip chip semiconductor die (105) and housed inside the device package to decouple noise from input signals, and a heat spreader (195) disposed between a top surface of the semiconductor die (105) and a package cover (185). The semiconductor die (105) is configured as a flip chip die and the device package includes a package substrate (110) configured as a ball grid array. The improved microelectronic device (100) reduces parasitic inductance in electrical interconnections between the semiconductor die and an electrical system substrate (115) and reduces signal noise in mixed signal high frequency analog to digital converters operating at clock rates above 1 GHz.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Applicant: Raytheon CompanyInventors: Dennis R. Kling, Bruce William Chignola, David J. Katz, Jorge M. Marcial, Leonard Schaper
-
Publication number: 20110317793Abstract: In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit configured to provide a feedback signal to a driver IC. The IC system also includes the driver IC configured to receive a second clock signal and includes a waveform generator configured to provide synthesized waveforms from DC to K-band, a serializer/deserializer (SERDES) to receive data from the waveform generator and to provide the signal to the receiver IC and a phase selection circuit to provide a phase selection signal to the first integrated circuit based on the feedback signal. The phase selection signal calibrates the signal from the SERDES and provides phase correction to the SERDES.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Applicant: Raytheon CompanyInventors: David J. Katz, Stephen R. Reid
-
Publication number: 20110316594Abstract: In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit to provide a feedback signal to a driver IC. The system also includes the driver IC configured to receive a second clock signal and includes a phase selection circuit configured to provide a phase selection signal to the receiver IC based on the feedback signal. The phase selection signal controls the data received by the receiver IC by adjusting the first clock signal.Type: ApplicationFiled: June 23, 2010Publication date: December 29, 2011Applicant: Raytheon CompanyInventors: Stephen R. Reid, David J. Katz
-
Patent number: 8067833Abstract: An improved microelectronic assembly (100) and packaging method includes a device package for housing a semiconductor die or chip, (105), an array of passive electronic components (305-355) operating in cooperation with the flip chip semiconductor die (105) and housed inside the device package to decouple noise from input signals, and a heat spreader (195) disposed between a top surface of the semiconductor die (105) and a package cover (185). The semiconductor die (105) is configured as a flip chip die and the device package includes a package substrate (110) configured as a ball grid array. The improved microelectronic device (100) reduces parasitic inductance in electrical interconnections between the semiconductor die and an electrical system substrate (115) and reduces signal noise in mixed signal high frequency analog to digital converters operating at clock rates above 1 GHz.Type: GrantFiled: July 23, 2009Date of Patent: November 29, 2011Assignee: Raytheon CompanyInventors: Dennis R. Kling, Bruce William Chignola, David J. Katz, Jorge M. Marcial, Leonard Schaper
-
Publication number: 20110018126Abstract: An improved microelectronic assembly (100) and packaging method includes a device package for housing a semiconductor die or chip, (105), an array of passive electronic components (305-355) operating in cooperation with the flip chip semiconductor die (105) and housed inside the device package to decouple noise from input signals, and a heat spreader (195) disposed between a top surface of the semiconductor die (105) and a package cover (185). The semiconductor die (105) is configured as a flip chip die and the device package includes a package substrate (110) configured as a ball grid array. The improved microelectronic device (100) reduces parasitic inductance in electrical interconnections between the semiconductor die and an electrical system substrate (115) and reduces signal noise in mixed signal high frequency analog to digital converters operating at clock rates above 1 GHz.Type: ApplicationFiled: July 23, 2009Publication date: January 27, 2011Applicant: Raytheon CompanyInventors: Dennis R. Kling, Bruce William Chignola, David J. Katz, Jorge M. Marcial, Leonard Schaper