Patents by Inventor David J. Keller
David J. Keller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9082721Abstract: The critical dimension (CD) of features formed during the fabrication of a semiconductor device may be controlled through the use of a dry develop chemistry comprising O2, SO2 and a hydrogen halide. For example, a dry develop chemistry comprising a gas comprising O2 and a gas comprising SO2 and a gas comprising HBr may be used to remove exposed areas of a carbon-based mask. The addition of HBr to the conventional O2 and SO2 dry develop chemistry enables a user to tune the critical dimension by growing, trimming and/or sloping the sidewalls and to enhance sidewall passivation and reduce sidewall bowing.Type: GrantFiled: February 4, 2013Date of Patent: July 14, 2015Assignee: Micron Technology, Inc.Inventors: David J. Keller, Alex Schrinsky
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Patent number: 8367303Abstract: The critical dimension (CD) of features formed during the fabrication of a semiconductor device may be controlled through the use of a dry develop chemistry comprising O2, SO2 and a hydrogen halide. For example, a dry develop chemistry comprising a gas comprising O2 and a gas comprising SO2 and a gas comprising HBr may be used to remove exposed areas of a carbon-based mask. The addition of HBr to the conventional O2 and SO2 dry develop chemistry enables a user to tune the critical dimension by growing, trimming and/or sloping the sidewalls and to enhance sidewall passivation and reduce sidewall bowing.Type: GrantFiled: July 14, 2006Date of Patent: February 5, 2013Assignee: Micron Technology, Inc.Inventors: David J. Keller, Alex Schrinsky
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Patent number: 8071441Abstract: Some embodiments include methods of forming transistor gates. A gate stack is placed within a reaction chamber and subjected to at least two etches, and to one or more depositions to form a transistor gate. The transistor gate may comprise at least one electrically conductive layer over a semiconductor material-containing layer. At least one of the one or more depositions may form protective material. The protective material may extend entirely across the at least one electrically conductive layer, and only partially across the semiconductor material-containing layer to leave unlined portions of the semiconductor material-containing layer. The unlined portions of the semiconductor material-containing layer may be subsequently oxidized.Type: GrantFiled: February 14, 2008Date of Patent: December 6, 2011Assignee: Micron Technology, IncInventor: David J. Keller
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Patent number: 8043911Abstract: The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing layer beneath the titanium-containing layer. The etch can utilize CH2F2. The silicon-containing layer can contain an n-type doped region and a p-type doped region. In some methods, the silicon-containing layer can contain an n-type doped region laterally adjacent a p-type doped region, and the processing can be utilized to form a transistor gate containing n-type doped silicon simultaneously with the formation of a transistor gate containing p-type doped silicon.Type: GrantFiled: January 10, 2008Date of Patent: October 25, 2011Assignee: Micron Technology, Inc.Inventor: David J. Keller
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Patent number: 7898019Abstract: Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.Type: GrantFiled: December 9, 2008Date of Patent: March 1, 2011Assignee: Micron Technology, Inc.Inventors: David J. Keller, Hongbin Zhu, Alex J. Schrinsky
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Publication number: 20090209072Abstract: Some embodiments include methods of forming transistor gates. A gate stack is placed within a reaction chamber and subjected to at least two etches, and to one or more depositions to form a transistor gate. The transistor gate may comprise at least one electrically conductive layer over a semiconductor material-containing layer. At least one of the one or more depositions may form protective material. The protective material may extend entirely across the at least one electrically conductive layer, and only partially across the semiconductor material-containing layer to leave unlined portions of the semiconductor material-containing layer. The unlined portions of the semiconductor material-containing layer may be subsequently oxidized.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Inventor: David J. Keller
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Publication number: 20090090958Abstract: Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.Type: ApplicationFiled: December 9, 2008Publication date: April 9, 2009Applicant: Micron Technology, Inc.Inventors: David J. Keller, Hongbin Zhu, Alex J. Schrinsky
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Patent number: 7476588Abstract: Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.Type: GrantFiled: January 12, 2007Date of Patent: January 13, 2009Assignee: Micron Technology, Inc.Inventors: David J. Keller, Hongbin Zhu, Alex J. Schrinsky
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Patent number: 7410748Abstract: A technique for etching with a single layered patterned photomask at wavelengths of 193 nanometers or less. Specifically, a method for etching a bottom anti-reflectant coating layer that utilizes a combination of CF4, CH2F2, and O2 to produce a stabilized pattern in the photoresist layer. The etching process results in a structure with a defined pattern having minimal defects and that maintains integrity through the remainder of the etching.Type: GrantFiled: August 31, 2004Date of Patent: August 12, 2008Assignee: Micron Technology, Inc.Inventor: David J. Keller
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Publication number: 20080169496Abstract: Some embodiments include methods of forming a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate. Some embodiments include utilization of an etch comprising HBr and O2 to extend a pattern through a carbon-containing layer. The patterned carbon-containing layer may be used to pattern NAND cell unit gates. Some embodiments include structures having a patterned carbon-containing layer defining a NAND cell unit having a NAND string gate closest to a select gate with a different width than other NAND string gates more distant from the select gate.Type: ApplicationFiled: January 12, 2007Publication date: July 17, 2008Inventors: David J. Keller, Hongbin Zhu, Alex J. Schrinsky
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Publication number: 20080132013Abstract: The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing layer beneath the titanium-containing layer. The etch can utilize CH2F2. The silicon-containing layer can contain an n-type doped region and a p-type doped region. In some methods, the silicon-containing layer can contain an n-type doped region laterally adjacent a p-type doped region, and the processing can be utilized to form a transistor gate containing n-type doped silicon simultaneously with the formation of a transistor gate containing p-type doped silicon.Type: ApplicationFiled: January 10, 2008Publication date: June 5, 2008Inventor: David J. Keller
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Patent number: 7341951Abstract: The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing layer beneath the titanium-containing layer. The etch can utilize CH2F2. The silicon-containing layer can contain an n-type doped region and a p-type doped region. In some methods, the silicon-containing layer can contain an n-type doped region laterally adjacent a p-type doped region, and the processing can be utilized to form a transistor gate containing n-type doped silicon simultaneously with the formation of a transistor gate containing p-type doped silicon.Type: GrantFiled: December 27, 2005Date of Patent: March 11, 2008Assignee: Micron Technology, Inc.Inventor: David J. Keller
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Publication number: 20080014533Abstract: The critical dimension (CD) of features formed during the fabrication of a semiconductor device may be controlled through the use of a dry develop chemistry comprising O2, SO2 and a hydrogen halide. For example, a dry develop chemistry comprising a gas comprising O2 and a gas comprising SO2 and a gas comprising HBr may be used to remove exposed areas of a carbon-based mask. The addition of HBr to the conventional O2 and SO2 dry develop chemistry enables a user to tune the critical dimension by growing, trimming and/or sloping the sidewalls and to enhance sidewall passivation and reduce sidewall bowing.Type: ApplicationFiled: July 14, 2006Publication date: January 17, 2008Inventors: David J. Keller, Alex Schrinsky
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Patent number: 7163017Abstract: A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features therein in spaced relation to each other which define an opening therebetween. A blanket polysilicon is formed over the wafer assembly and within the opening. A patterned photoresist layer is formed over the polysilicon layer, then the polysilicon layer within the opening is etched with a first etch. Subsequent to the first etch, the polysilicon with the opening is etched with a second etch comprising a halogen-containing gas flow rate of from about 35 sccm to about 65 sccm and an oxygen-containing gas (for example He—O2) flow rate of from about 12 sccm to about 15.6 sccm.Type: GrantFiled: April 20, 2004Date of Patent: January 16, 2007Assignee: Micron Technology, Inc.Inventor: David J. Keller
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Patent number: 6875559Abstract: A technique for etching with a single layered patterned photomask at wavelengths of 193 nanometers or less. Specifically, a method for etching a bottom anti-reflectant coating layer that utilizes a combination of CF4, CH2F2, and O2 to produce a stabilized pattern in the photoresist layer. The etching process results in a structure with a defined pattern having minimal defects and that maintains integrity through the remainder of the etching. A second etching process implementing an etchant having a high dielectric to photoresist selectivity may be used to further etch underlying layers.Type: GrantFiled: August 29, 2002Date of Patent: April 5, 2005Assignee: Micron Technology, Inc.Inventor: David J. Keller
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Publication number: 20040203243Abstract: A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features therein in spaced relation to each other which define an opening therebetween. A blanket polysilicon is formed over the wafer assembly and within the opening. A patterned photoresist layer is formed over the polysilicon layer, then the polysilicon layer within the opening is etched with a first etch. Subsequent to the first etch, the polysilicon with the opening is etched with a second etch comprising a halogen-containing gas flow rate of from about 35 sccm to about 65 sccm and an oxygen-containing gas (for example HeO2) flow rate of from about 12 sccm to about 15.6 sccm.Type: ApplicationFiled: April 20, 2004Publication date: October 14, 2004Inventor: David J. Keller
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Patent number: 6722376Abstract: A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features therein in spaced relation to each other which define an opening therebetween. A blanket polysilicon is formed over the wafer assembly and within the opening. A patterned photoresist layer is formed over the polysilicon layer, then the polysilicon layer within the opening is etched with a first etch. Subsequent to said first etch, the polysilicon with the opening is etched with a second etch comprising a halogen-containing gas flow rate of from about 35 sccm to about 65 sccm and an oxygen-containing gas (for example HeO2) flow rate of from about 12 sccm to about 15.6 sccm.Type: GrantFiled: December 10, 1999Date of Patent: April 20, 2004Assignee: Micron Technology, Inc.Inventor: David J. Keller
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Publication number: 20040043333Abstract: A technique for etching with a single layered patterned photomask at wavelengths of 193 nanometers or less. Specifically, a method for etching a bottom anti-reflectant coating layer that utilizes a combination of CF4, CH2F2, and O2 to produce a stabilized pattern in the photoresist layer. The etching process results in a structure with a defined pattern having minimal defects and that maintains integrity through the remainder of the etching.Type: ApplicationFiled: August 29, 2002Publication date: March 4, 2004Inventor: David J. Keller
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Patent number: 6552394Abstract: The invention encompasses a transistor device comprising a region of a semiconductor material, and a transistor gate over a portion of the region. The device comprises a pair of opposing sidewall spacers adjacent sidewalls of the transistor gate and a pair of opposing first conductivity type source/drain regions within the semiconductor material proximate the transistor gate. The entirety of the semiconductor material under one of the sidewall spacers being defined as a first segment, and the entirety of the semiconductor material which is under the other of the sidewall spacers being defined as a second segment. The first and second segments of the semiconductor material are separated from the first and second source/drain regions by first and second gap regions, respectively, of the semiconductor material. The device further comprises a pair of opposing second conductivity type halo regions within the first and second gap regions.Type: GrantFiled: November 29, 2001Date of Patent: April 22, 2003Assignee: Micron Technology, Inc.Inventors: Aftab Ahmad, David J. Keller
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Patent number: 6545308Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.Type: GrantFiled: March 5, 2002Date of Patent: April 8, 2003Assignee: Micron Technology, Inc.Inventors: David J. Keller, Louie Liu, Kris K. Brown