Abstract: This invention provides the ability to significantly lower the power consumed by a group of Ethernet links when organized in a Link Aggregation Group. When the server or switch senses low bandwidth utilization across multiple links in the group, it will negotiate the transition of un-necessary links to a lower power state. When the bandwidth requirements increases, the algorithm will quickly re-establish links and distribute the Ethernet traffic across the multiple links when necessary.

Abstract: A technique includes network booting a physical machine coupled to a network by a link aggregation group. The technique includes selectively disabling ports of the physical machine associated with the link aggregation group in connection with the network booting until a driver of an operating system to group the ports together is installed on the physical machine.

Abstract: A technique includes network booting a physical machine coupled to a network by a link aggregation group. The technique includes selectively disabling ports of the physical machine associated with the link aggregation group in connection with the network booting until a driver of an operating system to group the ports together is installed on the physical machine.

Abstract: Embodiments provide methods, apparatuses, and systems for transmitting an auto-negotiation message via one lane of a plurality of lanes to determine a link configuration between a first device and a second device, wherein the link configuration utilizes a plurality of lanes. In response to the auto-negotiation message, the network device may determine that one of the plurality of lanes is inoperative. The network device may then reconfigure the link configuration to utilize a subset of the plurality of lanes.

Abstract: A network device comprises a processor and storage coupled to the processor. The storage contains firmware that, when executed by the processor, causes the processor to implement a plurality of virtual devices. Each virtual device is configured to receive packets in a channel unique to such virtual device. The channels of the plurality of virtual devices are implemented on a single communication link. The network device is configured to receive a channel status message that is indicative of status of a channel corresponding to that message.

Abstract: This invention provides the ability to significantly lower the power consumed by a group of Ethernet links when organized in a Link Aggregation Group. When the server or switch senses low bandwidth utilization across multiple links in the group, it will negotiate the transition of un-necessary links to a lower power state. When the bandwidth requirements increases, the algorithm will quickly re-establish links and distribute the Ethernet traffic across the multiple links when necessary.

Abstract: A technique for improving performance in a multi-processor system by reducing access latency by correlating processor, node and memory allocation. Specifically, a Process/Thread Scheduler is modified such that system mapping and node proximity tables may be referenced to help determine processor assignments for ready-to-run processes/threads. Processors are chosen to minimize access latency. Further, the Page Fault Handler is modified such that free memory pages are assigned to a process based partially on the proximity of the memory with respect to the processor requesting memory allocation.

Abstract: A method and apparatus for distributing power to a plurality of computers in a network. A power management system including a feed-back mechanism, is employed to monitor power consumptions of the plurality of computers. Should the overall power consumption reach a threshold, the power management system instructs the microprocessors in the plurality of computers to enter into a lower power state, such as a sleep state, for a certain duration, thus lowering overall power.

Abstract: A technique for improving performance in a multi-processor system by reducing access latency by correlating processor, node and memory allocation. Specifically, a Process/Thread Scheduler is modified such that system mapping and node proximity tables may be referenced to help determine processor assignments for ready-to-run processes/threads. Processors are chosen to minimize access latency. Further, the Page Fault Handler is modified such that free memory pages are assigned to a process based partially on the proximity of the memory with respect to the processor requesting memory allocation.

Abstract: A technique for processing data packets in a network. Specifically, an expansion card is provided for a computer system. The expansion card is configured to be inserted into a computer system to facilitate network interface functions and security functions. By providing chipsets to perform network interface functions and security functions, on a single expansion card, secured data exchange over a network, such as the Internet, may be facilitated more efficiently.

Abstract: A method and apparatus for distributing power to a plurality of computers in a network. A power management system including a feed-back mechanism, is employed to monitor power consumptions of the plurality of computers. Should the overall power consumption reach a threshold, the power management system instructs the microprocessors in the plurality of computers to enter into a lower power state, such as a sleep state, for a certain duration, thus lowering overall power.

Abstract: A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of computer systems need no longer replace entire memory arrays to take advantage of new memory modules; some memory modules may be upgraded to a new type while other memory modules of an older type remain. The memory controller receives memory requests from multiple processors and bus masters, identifies a memory module and memory access parameters for each request, accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers or RAM personality modules that translate between the first memory controller and a particular type of memory module.

Abstract: A heat dissipating apparatus for use on a heat generating electric component inside a computer comprises an interposer mounted on the heat generating electric component and a heat absorbing member including a heat absorber, a bracing member, and a spring biasing said heat absorber toward the bracing member. The heat absorbing member is moveable between a first position in which the interposer is compressed between the heat absorber and the bracing member and a second position in which the interposer is not compressed between the heat absorber and the bracing member.

Abstract: A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of computer systems need no longer replace entire memory arrays to take advantage of new memory modules; some memory modules may be upgraded to a new type while other memory modules of an older type remain. The memory controller receives memory requests from multiple processors and bus masters, identifies a memory module and memory access parameters for each request, accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers or RAM personality modules that translate between the first memory controller and a particular type of memory module.

Abstract: A computer system includes a plurality of processor buses, and a memory bank. The plurality of processors is coupled to the processor buses. At least a portion of the processors have associated cache memories arranged in cache lines. The memory bank is coupled to the processor buses. The memory bank includes a main memory and a distributed coherency filter. The main memory is adapted to store data corresponding to at least a portion of the cache lines. The distributed coherency filter is adapted to store coherency information related to the cache lines associated with each of the processor buses. A method for maintaining cache coherency among processors coupled to a plurality of processor buses is provided. Lines of data are stored in a main memory. A memory request is received for a particular line of data in the main memory from one of the processor buses. Coherency information is stored related to the lines of data associated with each of the processor buses.

Abstract: A memory controller capable of supporting heterogeneous memory configurations enables seamless communications between a bus and memory modules having different characteristics. Thus, owners of computer systems need no longer replace entire memory arrays to take advantage of new memory modules; some memory modules may be upgraded to a new type while other memory modules of an older type remain. The memory controller receives memory requests from multiple processors and bus masters, identifies a memory module and memory access parameters for each request, accesses the memory and returns the resulting data (during a read request) or stores the data (during a write request). In some systems, the memory controller of the present invention is a two-tier memory controller system having a first memory controller coupled to the bus and to the second tier of memory controllers or RAM personality modules that translate between the first memory controller and a particular type of memory module.

Abstract: A combination support and heat sink structure is mounted within a computer housing for pivotal movement between connected and disconnected positions and includes a pair of cooling plates, one air cooled and the other liquid cooled, carried in a spaced apart, parallel opposing relationship. The two cooling plates are movable toward and away from one another and a pair of manually operable spring clip members permit a processor card to be removably sandwiched and clamped between the cooling plates without the use of tools.

Abstract: A combination support and heat sink structure is mounted within a computer housing for pivotal movement between connected and disconnected positions and includes a pair of cooling plates, one air cooled and the other liquid cooled, carried in a spaced apart, parallel opposing relationship. The two cooling plates are movable toward and away from one another and a pair of manually operable spring clip members permit a processor card to be removably sandwiched and clamped between the cooling plates without the use of tools.

Abstract: Operating heat from a computer microprocessor chip mounted on the top side of a printed circuit board is removed therefrom using a heat dissipation assembly including a metal heat transfer plate and a metal heat conductor block. The heat transfer plate is secured to the circuit board and has a first section which underlies the circuit board beneath the microprocessor chip, and a second portion projecting outwardly from an edge of the circuit board and secured to a wall of the metal housing cage of the computer. The metal heat conductor block extends through a complementarily configured opening formed in the circuit board beneath a central portion of the metal underside section of the chip.