Patents by Inventor David J. Lilja
David J. Lilja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11475288Abstract: Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.Type: GrantFiled: November 5, 2019Date of Patent: October 18, 2022Assignee: Regents of the University of MinnesotaInventors: Mohammadhassan Najafi, David J. Lilja, Marcus Riedel, Kiarash Bazargan
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Patent number: 11275563Abstract: Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.Type: GrantFiled: June 19, 2020Date of Patent: March 15, 2022Assignee: Regents of the University of MinnesotaInventors: Mohammadhassan Najafi, David J. Lilja, Marcus Riedel, Kiarash Bazargan, Sayed Abdolrasoul Faraji, Bingzhe Li
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Patent number: 11018689Abstract: In some examples, a device includes shuffling circuitry configured to receive an input unary bit stream and generate a shuffled bit stream by selecting n-tuple combinations of bits of the input unary bit stream. The device also includes stochastic logic circuitry having a plurality of stochastic computational units configured to perform operations on the shuffled bit stream in parallel to produce an output unary bit stream, each of the stochastic computational units operating on a different one of the n-tuple combinations of the bits.Type: GrantFiled: October 19, 2018Date of Patent: May 25, 2021Assignee: Regents of the University of MinnesotaInventors: Soheil Mohajer, Zhiheng Wang, Kiarash Bazargan, Marcus Riedel, David J. Lilja, Sayed Abdolrasoul Faraji
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Patent number: 10996929Abstract: This disclosure describes techniques for processing data bits using pseudo-random deterministic bit-streams. In some examples, a device includes a pseudo-random bit-stream generator configured to generate bit combinations encoding first and second numerical values based on a proportion of the data bits in the sequence that are high relative to the total data bits in the sequence. The device also includes a stochastic computational unit configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation, wherein the data bits of the output bit-stream represent the result based on a probability that any data bit in the set of data bits of the output bit-stream is high.Type: GrantFiled: March 14, 2019Date of Patent: May 4, 2021Assignee: Regents of the University of MinnesotaInventors: Mohammadhassan Najafi, David J. Lilja
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Publication number: 20200401376Abstract: Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.Type: ApplicationFiled: June 19, 2020Publication date: December 24, 2020Inventors: Mohammadhassan Najafi, David J. Lilja, Marcus Riedel, Kiarash Bazargan, Sayed Abdolrasoul Faraji, Bingzhe Li
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Patent number: 10740686Abstract: Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.Type: GrantFiled: January 12, 2018Date of Patent: August 11, 2020Assignee: Regents of the University of MinnesotaInventors: Mohammadhassan Najafi, Shiva Jamalizavareh, David J. Lilja, Marcus Riedel, Kiarash Bazargan, Ramesh Harjani
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Publication number: 20200143234Abstract: Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.Type: ApplicationFiled: November 5, 2019Publication date: May 7, 2020Inventors: Mohammadhassan Najafi, David J. Lilja, Marcus Riedel, Kiarash Bazargan
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Patent number: 10520975Abstract: In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.Type: GrantFiled: March 3, 2017Date of Patent: December 31, 2019Assignee: Regents of the University of MinnesotaInventors: David J. Lilja, Mohammadhassan Najafi, Marcus Riedel, Kiarash Bazargan
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Publication number: 20190289345Abstract: This disclosure describes techniques for processing data bits using pseudo-random deterministic bit-streams. In some examples, a device includes a pseudo-random bit-stream generator configured to generate bit combinations encoding first and second numerical values based on a proportion of the data bits in the sequence that are high relative to the total data bits in the sequence. The device also includes a stochastic computational unit configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation, wherein the data bits of the output bit-stream represent the result based on a probability that any data bit in the set of data bits of the output bit-stream is high.Type: ApplicationFiled: March 14, 2019Publication date: September 19, 2019Inventors: Mohammadhassan Najafi, David J. Lilja
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Publication number: 20190121839Abstract: In some examples, a device includes shuffling circuitry configured to receive an input unary bit stream and generate a shuffled bit stream by selecting n-tuple combinations of bits of the input unary bit stream. The device also includes stochastic logic circuitry having a plurality of stochastic computational units configured to perform operations on the shuffled bit stream in parallel to produce an output unary bit stream, each of the stochastic computational units operating on a different one of the n-tuple combinations of the bits.Type: ApplicationFiled: October 19, 2018Publication date: April 25, 2019Inventors: Soheil Mohajer, Zhiheng Wang, Kiarash Bazargan, Marcus Riedel, David J. Lilja, Sayed Abdolrasoul Faraji
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Publication number: 20180204131Abstract: Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.Type: ApplicationFiled: January 12, 2018Publication date: July 19, 2018Inventors: Mohammadhassan Najafi, Shiva Jamalizavareh, David J. Lilja, Marcus Riedel, Kiarash Bazargan, Ramesh Harjani
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Publication number: 20170255225Abstract: In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.Type: ApplicationFiled: March 3, 2017Publication date: September 7, 2017Inventors: David J. Lilja, Mohammadhassan Najafi, Marcus Riedel, Kiarash Bazargan
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Patent number: 8634233Abstract: Systems and methods that enable direct communications between magnetic tunnel junctions are provided. In one embodiment, a device includes multiple input magnetic tunnel junctions and an output magnetic tunnel junction. The multiple input magnetic tunnel junctions are connected in parallel, and the output magnetic tunnel junction is connected in series to the input magnetic tunnel junctions. In another embodiment, a device includes a first magnetic tunnel junction, a second magnetic tunnel junction, and a nano-magnetic channel. Each of the first and the second magnetic tunnel junctions has a free layer, a nonmagnetic layer, and a fixed layer. The nano-magnetic channel connects the free layer of the first magnetic tunnel junction to the free layer of the second magnetic tunnel junction.Type: GrantFiled: May 18, 2012Date of Patent: January 21, 2014Assignee: Regents of the University of MinnesotaInventors: David J. Lilja, Jian-Ping Wang, Andrew P. Lyle, Shruti R. Patil, Jonathan D. Harms, Xiaofeng Yao
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Publication number: 20120314489Abstract: Systems and methods that enable direct communications between magnetic tunnel junctions are provided. In one embodiment, a device includes multiple input magnetic tunnel junctions and an output magnetic tunnel junction. The multiple input magnetic tunnel junctions are connected in parallel, and the output magnetic tunnel junction is connected in series to the input magnetic tunnel junctions. In another embodiment, a device includes a first magnetic tunnel junction, a second magnetic tunnel junction, and a nano-magnetic channel. Each of the first and the second magnetic tunnel junctions has a free layer, a nonmagnetic layer, and a fixed layer. The nano-magnetic channel connects the free layer of the first magnetic tunnel junction to the free layer of the second magnetic tunnel junction.Type: ApplicationFiled: May 18, 2012Publication date: December 13, 2012Applicant: Regents of the University of MinnesotaInventors: David J. Lilja, Jian-Ping Wang, Andrew P. Lyle, Shruti R. Patil, Jonathan D. Harms, Xiaofeng Yao
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Publication number: 20080239948Abstract: Methods and apparatus are provided to improve data throughput in a wireless, wireline or a combination wireless and wireline communication system. A congestion control manager selects between an assumption based congestion control algorithm and a speculation based congestion control algorithm. The selected algorithm generates data recovery instructions including instructions for resizing, or not, congestion window sizing for the communication gateways. By making the selection between the assumption based congestion control algorithm and the speculation based congestion control algorithm based upon network information, data recovery and throughput is optimized for networks having lossy data links.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Applicant: HONEYWELL INTERNATIONAL, INC.Inventors: Haowei Bai, David J. Lilja
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Publication number: 20080239953Abstract: Methods and apparatus are provided to reduce data congestion and thus improve data throughput in gateways used in a wireless, wireline or a combination wireless and wireline communication system. The congestion management system optimally resizes, or not, congestion window (or buffer) sizing and threshold for the communication gateways based upon mathematical models. Application of the inventive congestion management method optimizes data recovery and throughput in communication networks, particularly those networks having lossy data links.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Applicant: HONEYWELL INTERNATIONAL, INC.Inventors: Haowei Bai, David J. Lilja
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Publication number: 20030182539Abstract: It has been determined that, in a superscalar computer processor, executing load instructions issued along an incorrectly predicted path of a conditional branch instruction eventually reduces the number of cache misses observed on the correct branch path. Executing these wrong-path loads provides an indirect prefetching effect. If the processor has a small L1 data cache, however, this prefetching pollutes the cache causing an overall slowdown in performance. By storing the execution results of mispredicted paths in memory, such as in a wrong path cache, the pollution is eliminated. A wrong path cache can improve processor performance up to 17% in simulations using a 32 KB data cache. A fully-associative eight-entry wrong path cache in parallel with a 4 KB direct-mapped data cache allows the execution of wrong path loads to produce an average processor speedup of 46%. The wrong path cache also results in 16% better speedup compared to the baseline processor equipped with a victim cache of the same size.Type: ApplicationFiled: March 20, 2002Publication date: September 25, 2003Applicant: International Business Machines CorporationInventors: Steven R. Kunkel, David J. Lilja, Resit Sendag
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Publication number: 20030005422Abstract: A method of improving a prediction rate for instructions in code includes determining a sequence from profile information; and transforming the code based on the determined sequence. A method of improving processor performance includes transforming a set of branches into a second set of branches, wherein the second set of branches comprises the original set of branches; and a sequence of branches likely to execute as an entity. A processor includes means for processing instructions; and means for transforming a set of branches into a second set of branches, wherein the second set of branches comprises the original set of branches; and a sequence of branches likely to execute as an entity.Type: ApplicationFiled: July 2, 2001Publication date: January 2, 2003Inventors: Nicolai Kosche, Chris Hescott, Qing Zhao, Youngsoo Choi, David J. Lilja
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Patent number: 4888684Abstract: A bus protocol system for interprocessor communications in valves polling the processors of a multiprocessor unit in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processor are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.Type: GrantFiled: March 28, 1986Date of Patent: December 19, 1989Assignee: Tandem Computers IncorporatedInventors: David J. Lilja, A. Richard Zacher, Steven W. Wierenga