Patents by Inventor David J. Lund

David J. Lund has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8055960
    Abstract: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: William V Huott, David J Lund, Kenneth H Marz, Bryan L Mechtly, Pradip Patel
  • Publication number: 20090204762
    Abstract: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.
    Type: Application
    Filed: February 7, 2008
    Publication date: August 13, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: William V. Huott, David J. Lund, Kenneth H. Marz, Bryan L. Mechtly, Pradip Patel
  • Patent number: 7529997
    Abstract: An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are defective, identify corresponding fuse repair values, proactively call home if spare fuses are not available, schedule soft fuse repairs for the next system restart, schedule line deletes at the next restart, store delete and fuse repairs in a table (tagged with electronic serial id, timestamp of delete or ABIST fail event, address, and type of failure) and proactively call home if there were any missed deletes that were not logged. Fuse information can also be more permanently stored into hardware electronic fuses and/or EPROMs. During a restart, previous repairs are able to be applied to the machine so that ABIST will run successfully and previous deletes to be maintained with checking to allow some ABIST failures which are protected by the line deletes to pass.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: May 5, 2009
    Assignee: International Business Machines Corporation
    Inventors: Patrick J. Meaney, William V. Huott, Thomas J. Knips, David J. Lund, Bryan L. Mechtly, Pradip Patel
  • Patent number: 7366953
    Abstract: A computing system is provided which includes a processor having a cache memory. The cache memory includes a plurality of independently configurable subdivisions, each subdivision including a memory array. A service element (SE) of the computing system is operable to cause a built-in-self-test (BIST) to be executed to test the cache memory, the BIST being operable to determine whether any of the subdivisions is defective. When it is determined that one of the subdivisions of the cache memory determined defective by the BIST is non-repairable, the SE logically deletes the defective subdivision from the system configuration, and the SE is operable to permit the processor to operate without the logically deleted subdivision. The SE is further operable to determine that the processor is defective when a number of the defective subdivisions exceeds a threshold.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: April 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: William V. Huott, David J. Lund, Kenneth H. Marz, Bryan L. Mechtly, Pradip Patel
  • Patent number: 4413890
    Abstract: An apparatus for objectively detecting ocular disorders adapted to the expedient examination of uncooperative patients generally comprises structures for collimating light into two predetermined paths for coaxial illumination of a person's right and left eye; structures for conditioning the collimated light; apertures for illuminating and retroflecting the collimated light by a person's eyes; and structures for detecting the relative intensities of the retroflected collimated light. A method for expediently examining uncooperative patients adapted to objectively detecting an ocular disorder comprises coaxially illuminating each eye; effecting a relative position between the apertures of an apparatus and a patient'eyes so that brief illuminating contact with the collimated light is effected; retroflecting the collimating light illuminating each eye; and measuring the relative intensities of the retroflected collimated light so that ocular disorders can be objectively determined.
    Type: Grant
    Filed: March 20, 1981
    Date of Patent: November 8, 1983
    Inventors: Michael Belkin, David J. Lund