Abstract: A free radical curable automotive body primer is provided that has a color change corresponding to the progress of the cure process until a dry to sand condition has been attained and an internal colored guide coat that does not change color given its exposure to ambient air and as a result, has a different color on the surface of the primer than when in bulk, allowing for the detection and removal of low spots or other imperfections from a vehicle body by additional sanding of the inventive primer to remove oxidized guide coat colorant surface regions. The cure color change is achieved through resort to at least one color changing dye that reacts with a free radical cure initiator during the vehicle body priming process and changes color to indicate when the primer composition has achieved a level of cure so as to be dry enough to sand.

Abstract: A free radical curable automotive body primer is provided that has a color change corresponding to the progress of the cure process until a dry to sand condition has been attained and an internal colored guide coat that does not change color given its exposure to ambient air and as a result, has a different color on the surface of the primer than when in bulk, allowing for the detection and removal of low spots or other imperfections from a vehicle body by additional sanding of the inventive primer to remove oxidized guide coat colorant surface regions. The cure color change is achieved through resort to at least one color changing dye that reacts with a free radical cure initiator during the vehicle body priming process and changes color to indicate when the primer composition has achieved a level of cure so as to be dry enough to sand.

Abstract: A logic analyzer uses a single tapped delay line and a single array of sampling cells for high speed digital signal acquisition, by controlling both edges of a substantially 50% duty cycle clock signal to drive a delay line buffer chain. The chain operates continuously; there being no need for interruptions for precharge intervals. Thus, the need for a second delay line buffer chain is eliminated.

Abstract: A first comparison circuit compares an internally generated clock signal with a reference signal and produces a first error signal in response to timing differences between rising edges of the clock signal and the reference signal. A second comparison circuit compares the internally generated clock signal with the reference signal and produces a second error signal in response to timing differences between falling edges of the clock signal and the reference signal. The first and second error signals are applied to control inputs of a phase shifter chain to control delay in each stage to reduce the timing error with respect to each edge.

Abstract: A programmable delay circuit with a simplified structure conserves parts and provides for simplified programmability. In this structure, N delay stages (1-N) each include delay elements (10,26, . . . ,80) that produce delay times that are related as powers of two and are connected by two-input multiplexers (12,22, . . . ,82). The two-input multiplexers select between the input and output of the delay element in their stage, and are collectively controlled by N-bits of delay selection signals that are connected so that less significant bits control multiplexers associated with delay elements producing shorter delays and more significant bits control multiplexers associated with delay elements producing longer delays in a monotonic correspondence. The resulting structure conserves parts and produces an overall delay time that is directly proportional to the binary value used to control the multiplexers.

Abstract: An accurate delay generator circuit for delaying the rising and falling edge of an input signal includes: a current switch having an input for receiving the input signal, first and second current inputs, and a current output; a p-channel transistor coupled to the first current input of the current switch; a first threshold voltage generator coupled to the gate of the p-channel transistor for generating a voltage equal to twice a p-channel threshold voltage with respect to VDD; an n-channel transistor coupled to the second current input of the current switch; a second threshold voltage generator coupled to the gate of the n-channel transistor for generating a voltage equal to twice an n-channel thresold voltage with respect to ground; a capacitor coupled to the output of the current switch; and an output inverter stage coupled to the output of the current switch for providing the delayed input signal.