Patents by Inventor David J. Megaw

David J. Megaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7453252
    Abstract: A circuit includes a bandgap core and a bandgap amplifier. The bandgap core is capable of receiving an input voltage and generating an output voltage. A second-order temperature coefficient in the output voltage is at least partially reduced by the bandgap core while a first-order temperature coefficient in the output voltage remains substantially unchanged.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: November 18, 2008
    Assignee: National Semiconductor Corporation
    Inventor: David J. Megaw
  • Patent number: 7019590
    Abstract: A circuit for providing a self-stabilizing, differential load circuit with well controlled impedance to an amplifier is described. According to one embodiment, two pairs of transistors in a cross-coupled configuration and a degeneration resistor for each transistor provide the self-stabilizing, differential load. Small signal analysis of the circuit illustrates an impedance of the load circuit to be substantially equal to a combination of resistor values with substantially little dependence on transconductances and incremental resistances of the transistors. By employing well matched resistors, impedance of the load to the amplifier may be well controlled, and common mode feedback loops avoided, because a current source is not employed as a load. Furthermore, due to use of transistors, a low voltage headroom may be increased and an integrated circuit area decreased.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: March 28, 2006
    Assignee: National Semiconductor Corporation
    Inventor: David J. Megaw
  • Patent number: 7015746
    Abstract: A biasing circuit is arranged to provide relatively well controlled startup and steady state behavior for a reference circuit such as noise immunity and reduced dependence on supplies. The biasing circuit initially employs an independent bias current for biasing the reference circuit at startup until a large enough bootstrapped (output voltage referenced) bias current can be generated that can take over the subsequent biasing of the circuit in the steady state. In one embodiment, a Power On Reset (POR) signal can be generated during the transition from an initial biasing of the reference circuit by the independent bias current to a subsequent steady state biasing provided by the bootstrapped bias current. Also, the assertion of the POR signal can be employed to turn off the transistors providing the independent bias current.
    Type: Grant
    Filed: May 6, 2004
    Date of Patent: March 21, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Steve A. Martinez, Paul D. Ranucci, David J. Megaw