Patents by Inventor David J. Palframan

David J. Palframan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Energy efficient optimization in multicore processors under quality of service (QoS)/performance constraints
    Patent number: 9541985
    Abstract: A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: January 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Heather L. Hanson, David J. Palframan, Srinivasan Ramani, Ken V. Vu
  • Energy efficient optimization in multicore processors under quality of service (QoS)/performance constraints
    Patent number: 9535486
    Abstract: A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Heather L. Hanson, David J. Palframan, Srinivasan Ramani, Ken V. Vu
  • Energy Efficient Optimization in Multicore Processors Under Quality of Service (QoS)/Performance Constraints
    Publication number: 20150169032
    Abstract: A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of sendee (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and die state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 18, 2015
    Applicant: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Heather L. Hanson, David J. Palframan, Srinivasan Ramani, Ken V. Vu
  • Energy Efficient Optimization in Multicore Processors Under Quality of Service (QoS)/Performance Constraints
    Publication number: 20150169035
    Abstract: A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.
    Type: Application
    Filed: June 13, 2014
    Publication date: June 18, 2015
    Inventors: Malcolm S. Allen-Ware, Heather L. Hanson, David J. Palframan, Srinivasan Ramani, Ken V. Vu