Abstract: The present invention relates to a single-board processor card configured for use in a 1U CubeSat payload form-factor multi-purpose architecture, including: a field-programmable-gate-array (FPGA) which is reconfigurable in flight; wherein a configuration memory of the FPGA can be scrubbed in flight to correct errors or upsets; and a radiation-hardened monitor (RHM) which provides radiation mitigation and system monitoring of the single-board processor card, and which reconfigures said FPGA during flight, scrubs the configuration memory, and monitors a health of the FPGA. The 1U CubeSat payload form-factor multi-purpose architecture includes a backplane having a plurality of slots, one of the plurality of slots which accommodates the single-board processor card, wherein the backplane routes signals to a plurality of standard-sized processor cards, interchangeably disposed in any of the plurality of slots.

Abstract: The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.

Abstract: The present invention relates to a Robot Electronics Unit (REU) motor controller board (MCB) with a trapezoid wave design, which can utilize power efficiently and reduce electromagnetic interference. The MCB uses a modulator or Buck Converter to regulate the voltage before it is passed to the motors used in robotic arms in space applications. The REU MCB includes: a commutator disposed on the MCB and connected to a three-phase induction motor; and a modulator disposed on the MCB and which precedes the commutator, the modulator which utilizes pulse width modulation (PWM) to regulate a voltage to the commutator and provide a predetermined current to the commutator. The modulator regulates the voltage by stepping it down from a 100V power input signal before the voltage is passed to the motor. The output of the modulator includes a trapezoid waveform design which controls the motor and reduces electromagnetic interference.

Abstract: An electronic assembly support system includes a frame having a plurality of side rails side rails to be positioned along a longitudinal axis of an electronic assembly, a plurality of cross rails connected between the side rails, positioned to surround predetermined components of the electronic assembly, and a first fastener interface for attaching the plurality of side rails and cross rails to the electronic assembly.

Abstract: The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.

Abstract: Aspects of the present disclosure involve a system and method for sampling received signals for performing time of flight estimation using LiDAR signal processing. In one aspect, a radio frequency analog-to-digital converter is used for real time waveform digitalization. The radio frequency analog-to-digital converter may be coupled to a mezzanine card and used to generate a clock for the converter. The digital waveform may then be buffered and correlated for time of flight estimation.

Abstract: A single board computer system radiation hardened for space flight includes a printed circuit board having a top side and bottom side; a reconfigurable field programmable gate array (FPGA) processor device disposed on the top side; a connector disposed on the top side; a plurality of peripheral components mounted on the bottom side; and wherein a size of the single board computer system is not greater than approximately 7 cm×7 cm.

Abstract: A stacking pin alignment fixture for a stacking connector includes a substrate and a plurality of openings defined in the substrate, the plurality of openings being arranged in a predefined pattern. The predefined pattern corresponds to a pattern of a field of straight pins arranged on the stacking connector.

Abstract: A low power voltage control circuit for use in space missions includes a switching device coupled between an input voltage and an output voltage. The switching device includes a control input coupled to an enable signal, wherein the control input is configured to selectively turn the output voltage on or off based at least in part on the enable signal. A current monitoring circuit is coupled to the output voltage and configured to produce a trip signal, wherein the trip signal is active when a load current flowing through the switching device is determined to exceed a predetermined threshold and is inactive otherwise. The power voltage control circuit is constructed of space qualified components.

Abstract: Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

Abstract: Apparatus for in-system emulation of a target non-volatile memory device, such as a target PROM that stores FPGA configuration files and general data. The in-system emulation apparatus serves as stand-in hardware for the target PROM within the target system, mounted within a surface mount footprint and within volume constraints of the target PROM in the target system. The apparatus for in-system PROM emulation includes a device converter, and a surface mount emulator foot. The device converter includes at least one reprogrammable memory device, which stores developmental data that emulates data stored by the target PROM. The device converter includes a device converter circuit board, secured to the surface mount emulator foot. The device converter may include four Flash PROM reprogrammable devices, mounted above and below the device converter circuit board. The surface mount emulator foot includes an emulator foot circuit board, and a surface mount package emulation adapter.

Abstract: An electronic assembly for use in space missions that includes a PCB and one or more multi-pin CGA devices coupled to the PCB. The PCB has one or more via-in-pad features and each via-in-pad feature comprises a land pad configured to couple a pin of the one or more multi-pin CGA devices to the via. The PCB also includes a plurality of layers arranged symmetrically in a two-halves configuration above and below a central plane of the PCB.

Abstract: Embodiments may provide a radiation hardened 10BASE-T Ethernet interface circuit suitable for space flight and in compliance with the IEEE 802.3 standard for Ethernet. The various embodiments may provide a 10BASE-T Ethernet interface circuit, comprising a field programmable gate array (FPGA), a transmitter circuit connected to the FPGA, a receiver circuit connected to the FPGA, and a transformer connected to the transmitter circuit and the receiver circuit. In the various embodiments, the FPGA, transmitter circuit, receiver circuit, and transformer may be radiation hardened.

Abstract: An on-board space processing system capable of processing data at more than 2500 Million Instructions Per Second on board a spacecraft is disclosed. The system may be a cube, and may include processor card and a hybrid card. The processor card may include a processor that may be programmable and reprogrammable prior to, and during, spaceflight. The hybrid card may include a field programmable gate array module that may program and reprogram the processor prior to, and during, the spaceflight.

Abstract: A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data.

Abstract: A processing system having a small form factor and configured to connect to an external platform. The processing system includes input interfaces configured to receive an input signal to be processed; a radiation tolerant field programmable gate array including processors configured to process the input signal; memory containing reconfigurable instructions for the processors that, when the reconfigurable instructions are executed, process the input signal and obtain the output signal; output interfaces configured to send the output signal to the external platform; and a reset logic element configured to selectively reset the field programmable gate array and at least one of the processors in response to a reset command. The input interfaces include at least one gigabit Ethernet interface and at least one space-rated balanced voltage digital interface circuit.