Patents by Inventor David J. Reilly
David J. Reilly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152189Abstract: Examples described in this disclosure relate to sub-kelvin control systems and methods for scalable quantum control. An example system includes a first cooling sub-system operable to maintain an operating temperature for a first device within a first sub-kelvin temperature range. The system further includes a second cooling sub-system, separate from the first cooling sub-system, operable to maintain an operating temperature for a second device, different from the first device, within a second sub-kelvin temperature range. The first sub-kelvin range may comprise a range between 50 milli-kelvin (mK) to 999 mK and the second sub-kelvin range may comprise a range between 1 mK to 299 mK. The combination of the first cooling sub-system and the second cooling sub-system is configured to maintain a temperature gradient between the first device and the second device despite the first device and the second device being in close proximity to each other.Type: ApplicationFiled: February 20, 2023Publication date: May 9, 2024Inventors: David J. REILLY, Ian Douglas CONWAY LAMB, Kushal DAS, Rachpon KALRA
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Patent number: 11838022Abstract: Systems and methods related to a cryogenic-CMOS interface for controlling qubit gates are provided. A system for controlling qubit gates includes a first device comprising a quantum device including qubit gates. The system further includes a second device comprising a control system configured to operate at the cryogenic temperature. The control system includes charge locking circuits, where each of the charge locking circuits is coupled to at least one qubit gate via an interconnect such that each of the charge locking circuits is configured to provide a voltage signal to at least one qubit gate. The control system further includes a control circuit comprising a finite state machine configured to provide at least one control signal to selectively enable at least one of the charge locking circuits and to selectively enable a provision of a voltage signal to a selected one of the charge locking circuit.Type: GrantFiled: December 5, 2019Date of Patent: December 5, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Kushal Das, Alireza Moini, David J. Reilly
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Patent number: 11831313Abstract: Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.Type: GrantFiled: October 14, 2022Date of Patent: November 28, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Kushal Das, Alireza Moini, David J. Reilly
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Patent number: 11824505Abstract: Systems and methods related to a parametric amplifier including a quantum capacitor are described. In one example, a parametric amplifier comprising an input terminal for receiving a qubit signal is provided. The parametric amplifier further includes a pump terminal for receiving a pump signal. The parametric amplifier further comprises an amplifier, including a plurality of quantum capacitance devices configured to operate in a cryogenic environment, configured to amplify the qubit signal by mixing the qubit signal with the pump signal to generate an amplified signal. The parametric amplifier further includes an output terminal for providing the amplified signal.Type: GrantFiled: December 8, 2020Date of Patent: November 21, 2023Assignee: Microsoft Technology Licensing, LLCInventor: David J. Reilly
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Publication number: 20230070500Abstract: Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.Type: ApplicationFiled: October 14, 2022Publication date: March 9, 2023Inventors: Kushal DAS, Alireza MOINI, David J. REILLY
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Patent number: 11601128Abstract: Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system includes a plurality of devices configured to operate in a cryogenic environment, where a first distribution of a threshold voltage associated with the plurality of devices has a first value indicative of a measure of spread of the threshold voltage. The system further includes control logic, coupled to each of the plurality of devices, configured to modify a threshold voltage associated with each of the plurality of devices such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage representing a lower variation among threshold voltages of the plurality of devices.Type: GrantFiled: May 13, 2022Date of Patent: March 7, 2023Assignee: Microsoft Technology Licensing, LLCInventor: David J. Reilly
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Patent number: 11509310Abstract: Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.Type: GrantFiled: December 5, 2019Date of Patent: November 22, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Kushal Das, Alireza Moini, David J. Reilly
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Publication number: 20220278686Abstract: Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system includes a plurality of devices configured to operate in a cryogenic environment, where a first distribution of a threshold voltage associated with the plurality of devices has a first value indicative of a measure of spread of the threshold voltage. The system further includes control logic, coupled to each of the plurality of devices, configured to modify a threshold voltage associated with each of the plurality of devices such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage representing a lower variation among threshold voltages of the plurality of devices.Type: ApplicationFiled: May 13, 2022Publication date: September 1, 2022Inventor: David J. REILLY
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Patent number: 11362665Abstract: Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system includes a plurality of devices configured to operate in a cryogenic environment, where a first distribution of a threshold voltage associated with the plurality of devices has a first value indicative of a measure of spread of the threshold voltage. The system further includes control logic, coupled to each of the plurality of devices, configured to modify a threshold voltage associated with each of the plurality of devices such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage representing a lower variation among threshold voltages of the plurality of devices.Type: GrantFiled: September 8, 2020Date of Patent: June 14, 2022Assignee: Microsoft Technology Licensing, LLCInventor: David J. Reilly
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Publication number: 20220182027Abstract: Systems and methods related to a parametric amplifier including a quantum capacitor are described. In one example, a parametric amplifier comprising an input terminal for receiving a qubit signal is provided. The parametric amplifier further includes a pump terminal for receiving a pump signal. The parametric amplifier further comprises an amplifier, including a plurality of quantum capacitance devices configured to operate in a cryogenic environment, configured to amplify the qubit signal by mixing the qubit signal with the pump signal to generate an amplified signal. The parametric amplifier further includes an output terminal for providing the amplified signal.Type: ApplicationFiled: December 8, 2020Publication date: June 9, 2022Inventor: David J. REILLY
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Publication number: 20220077859Abstract: Systems and methods related to low power cryo-CMOS circuits with non-volatile threshold voltage offset compensation are provided. A system includes a plurality of devices configured to operate in a cryogenic environment, where a first distribution of a threshold voltage associated with the plurality of devices has a first value indicative of a measure of spread of the threshold voltage. The system further includes control logic, coupled to each of the plurality of devices, configured to modify a threshold voltage associated with each of the plurality of devices such that the first distribution is changed to a second distribution having a second value of the measure of spread of the threshold voltage representing a lower variation among threshold voltages of the plurality of devices.Type: ApplicationFiled: September 8, 2020Publication date: March 10, 2022Inventor: David J. REILLY
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Publication number: 20200394548Abstract: Systems and methods related to a cryogenic-CMOS interface for controlling qubit gates are provided. A system for controlling qubit gates includes a first device comprising a quantum device including qubit gates. The system further includes a second device comprising a control system configured to operate at the cryogenic temperature. The control system includes charge locking circuits, where each of the charge locking circuits is coupled to at least one qubit gate via an interconnect such that each of the charge locking circuits is configured to provide a voltage signal to at least one qubit gate.Type: ApplicationFiled: December 5, 2019Publication date: December 17, 2020Inventors: Kushal Das, Alireza Moini, David J. Reilly
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Publication number: 20200395943Abstract: Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.Type: ApplicationFiled: December 5, 2019Publication date: December 17, 2020Inventors: Kushal Das, Alireza Moini, David J. Reilly
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Patent number: 8148715Abstract: This invention concerns a quantum device, suitable for quantum computing, based on dopant atoms located in a solid semiconductor or insulator substrate. In further aspects the device is scaled up. The invention also concerns methods of reading out from the devices, initializing them, using them to perform logic operations and making them.Type: GrantFiled: February 19, 2010Date of Patent: April 3, 2012Assignee: Quocor Pty. Ltd.Inventors: Lloyd Christopher Leonard Hollenberg, Andrew Steven Dzurak, Cameron Wellard, Alexander Rudolf Hamilton, David J. Reilly, Gerard J. Milburn, Robert Graham Clark
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Publication number: 20110049475Abstract: This invention concerns a quantum device, suitable for quantum computing, based on dopant atoms located in a solid semiconductor or insulator substrate. In further aspects the device is scaled up. The invention also concerns methods of reading out from the devices, initializing them, using them to perform logic operations and making them.Type: ApplicationFiled: February 19, 2010Publication date: March 3, 2011Inventors: Lloyd Christopher Leonard Hollenberg, Andrew Steven Dzurak, Cameron Wellard, Alexander Rudolf Hamilton, David J. Reilly, Gerard J. Milburn, Robert Graham Clark
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Patent number: 7732804Abstract: Ionisation of one of a pair of dopant atoms in a substrate creates a double well potential, and a charge qubit is realised by the location of one or more electrons or holes within this potential. The dopant atoms may comprise phosphorous atoms, located in a silicon substrate. A solid state quantum computer may be formed using a plurality of pairs of dopant atoms, corresponding gate electrodes, and read-out devices comprising single electron transistors.Type: GrantFiled: August 20, 2003Date of Patent: June 8, 2010Assignee: Quocor Pty. Ltd.Inventors: Lloyd Christopher Leonard Hollenberg, Andrew Steven Dzurak, Cameron Wellard, Alexander Rudolf Hamilton, David J. Reilly, Gerard J. Milburn, Robert Graham Clark