Abstract: The present disclosure relates to a field effect transistor (FET) structure. The FET structure has a substrate, an active region, a dielectric layer provided over a channel of the active region and a gate provided over the dielectric layer. The active region comprises a source, a drain and the channel provided between the source and the drain. The active region is surrounded by an isolation trench, such that width edges of the channel are directly adjacent to the isolation trench. Current paths run between the source and the drain, through the channel. The FET is configured such that current paths running proximal to the channel edges are reduced or weaker in comparison to a dominant current path running through a center of the channel. One or more of the channel, the dielectric layer or the substrate can be modified or adapted to provide the reduced and dominant current paths.

Abstract: The present disclosure relates to a field effect transistor (FET) structure. The FET structure has a substrate, an active region, a dielectric layer provided over a channel of the active region and a gate provided over the dielectric layer. The active region comprises a source, a drain and the channel provided between the source and the drain. The active region is surrounded by an isolation trench, such that width edges of the channel are directly adjacent to the isolation trench. Current paths run between the source and the drain, through the channel. The FET is configured such that current paths running proximal to the channel edges are reduced or weaker in comparison to a dominant current path running through a center of the channel. One or more of the channel, the dielectric layer or the substrate can be modified or adapted to provide the reduced and dominant current paths.