Patents by Inventor David J. Schanin

David J. Schanin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6243626
    Abstract: An external power-management device controls the supply of electric power from a wall outlet to a refrigerated vending machine. The system includes a switch that couples power in an ON condition and decouples in an OFF condition. The switch is controlled by a controller based on data received from a current sensor, an occupancy sensor, a temperature sensor, and a time-of-year circuit. Upon startup, the current is monitored to determine maxima and minima for the vending machine. The system supplies power to the appliance during business hours as indicated by the time-of-year circuit and while the vicinity is occupied as determined by the occupancy sensor irrespective of the values for current and temperature. Absent the current sensor, the power would be decoupled after a predetermined duration of non-occupancy during nonbusiness hours.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: June 5, 2001
    Assignee: Bayview Technology Group, Inc.
    Inventor: David J. Schanin
  • Patent number: 5477476
    Abstract: A power conservation system (PCS) includes a data handler, a controller and a power switch. The data handler is located between a host network and a network printer, while the power switch is between an AC power source and the printer's power input. The PCS can thus shut down the printer during periods when no data is being sent to the printer. The PCS monitors data to and from the printer, allowing it to track the printer's state and to capture its network identification. State tracking permits the PCS to emulate the printer when it is down and when it is booting. Additionally, the information stored in a state memory of the data handler can permit the printer's last ready state to be reconstructed after it turns on and boots to a ready state. In some cases, the data handler can answer network requests without turning on the printer. Thus, the PCS provides for effective power conservation while remaining invisible to a user.
    Type: Grant
    Filed: July 14, 1993
    Date of Patent: December 19, 1995
    Assignee: Bayview Technology Group, Inc.
    Inventors: David J. Schanin, Richard R. Billig
  • Patent number: 5239255
    Abstract: A phase-controlled power modulation system switches modes in response to circuit-threatening conditions to avert the necessity of a shutdown. Normal operation is in reverse phase control (RPC) mode. When an inductive load sensor detects the presence an inductive load, the system switches to a forward phase control (FPC) mode (FPC) to minimize voltage spikes that would otherwise result from the load's opposition to voltage transitions. When an overcurrent sensor detects an overcurrent, the system switches into an asymmetric hybrid mode (AHPC) to maximize delivered power while remaining within switch current handling capacity. In AHPC mode, an RPC component of a half-cycle waveform is cut off at the current limit, while an FPC component of the same half-cycle waveform is triggered after the source voltage drops to a confidence threshold below the current limit to ensure that current limiting is not triggered again during the same half-cycle.
    Type: Grant
    Filed: February 20, 1991
    Date of Patent: August 24, 1993
    Assignee: Bayview Technology Group
    Inventors: David J. Schanin, Richard R. Billig
  • Patent number: 5067071
    Abstract: Disclosed is a multiprocessor computer system including a plurality of processor modules with each of the processor modules including at least one processor and a cache memory which is shared by all of the processors of each processor module. The processor modules are connected to a system bus which comprises independent data, address, vectored interrupt, and control buses. A system memory which is shared by all the processor modules is also connected to the buses, and the cache memories in each processor module store those memory locations in the main memory most frequently accessed by the processors in its module. A system control module controls the operation and interaction of all of the modules and contains the bus arbiters for the vector, data and address buses. The system control module also controls the retrying of requests which are not completed and should any requester fail to obtain access to a bus, the system control module also unjams this deadlock.
    Type: Grant
    Filed: February 27, 1985
    Date of Patent: November 19, 1991
    Assignee: Encore Computer Corporation
    Inventors: David J. Schanin, Russel L. Moore, John R. Bartlett, Charles S. Namias, David W. Zopf, Brian D. Gill, Trevor A. Creary, Stephen S. Corbin, Mark J. Matale, David F. Ford, Steven J. Frank
  • Patent number: 5004969
    Abstract: A method and circuit for reverse phase control of alternating current being delivered to a load are disclosed wherein voltage-controlled semiconductor switches, such as MOSFET's and IGBT's, are used as electronic switches to conduct voltage during the leading edge of the AC voltage cycle and conduction is terminated when the desired phase angle of the current flow has been reached. The disclosed method and circuit eliminate the need for zero crossing detection of the AC waveform and ensure that the voltage-controlled switches are always turned on before the zero crossing thereby minimizing radiated interference and incandescent lamp hum. The method used is primarily digital in nature making mechanical input or electronic input for the power control equally efficient to implement.
    Type: Grant
    Filed: October 16, 1989
    Date of Patent: April 2, 1991
    Assignee: Bayview Technology Group, Inc.
    Inventor: David J. Schanin
  • Patent number: 4670855
    Abstract: The present structure is an interchangeable interface circuit card which per se includes: circuitry which is responsive to being addressed in accordance with its physical location; circuitry to generate signals which identify the circuit being addressed and the peripheral to which it is connected; and circuitry to generate signals which effect a diagnostic routine applicable to at least some of the interchangeable interface circuits on the circuit card being addressed. In addition the present structure includes priority circuitry which operates in conjunction with a data handling system to assert a priority value assigned to the interchangeable interface circuit card and which, based on that priority, determines which one of a number of interchangeable interface circuit cards will be permitted to control a common data path.
    Type: Grant
    Filed: October 18, 1985
    Date of Patent: June 2, 1987
    Assignee: Digital Equipment Corporation
    Inventors: A. Ronald Caprio, John P. Cyr, Bernard O. Geaghan, Paul C. Kotschenreuther, David J. Schanin, Ronald M. Salett
  • Patent number: 4556953
    Abstract: The present disclosure is directed to an arrangement whereby any one of a plurality of different or similar interface circuit cards can be located into any one of a number of slots or holding means of a data processing system, without preassignment thereto, and whereby each of the interface circuit cards will generate its own diagnostic routine signals and signals representing its own identification, the latter signals being used in a self-configuration operation of the system and whereby an arbiter means is employed to determine, among the plurality of interface circuits, which has the highest priority in the event more than one of said interface circuits is requesting the use of a common data flow path.
    Type: Grant
    Filed: February 24, 1982
    Date of Patent: December 3, 1985
    Inventors: A. Ronald Caprio, John P. Cyr, Bernard O. Geaghan, Paul C. Kotschenreuther, David J. Schanin, Ronald M. Salett
  • Patent number: 4446382
    Abstract: The present disclosure describes a circuit arrangement wherein a clock signal generator generates two sets of time-period, separated enable signals and wherein there is controllable first direction current flow circuitry and controllable second direction current flow circuitry. One set of said enable signals is connected to said first circuitry to cause current flow in a first direction during a first period of time while the other set of said enable signals is connected to said second circuitry to cause current flow in a second direction during a second period of time which is separated from said first period by a predetermined period. The arrangement insures that the circuitry will not attempt to drive current in both directions at the same time.
    Type: Grant
    Filed: February 24, 1982
    Date of Patent: May 1, 1984
    Inventors: Russell L. Moore, David J. Schanin
  • Patent number: RE33705
    Abstract: The present structure is an interchangeable interface circuit card which per se includes: circuitry which is responsive to being addressed in accordance with its physical location; circuitry to generate signals which identify the circuit being addressed and the peripheral to which it is connected; and circuitry to generate signals which effect a diagnostic routine applicable to at least some of the interchangeable interface circuits on the circuit card being addressed. In addition the present structure includes priority circuitry which operates in conjunction with a data handling system to assert a priority value assigned to the interchangeable interface circuit card and which, based on that priority, determines which one of a number of interchangeable interface circuit cards will be permitted to control a common data path.
    Type: Grant
    Filed: May 6, 1988
    Date of Patent: October 1, 1991
    Assignee: Digital Equipment Corporation
    Inventors: A. Ronald Caprio, John P. Cyr, Bernard O. Geaghan, Paul C. Kotschenreuther, David J. Schanin, Ronald M. Salett