Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

Abstract: A method of transmitting data through a link comprises encoding digital data into encoded digital data in a transition minimized differential signaling encoder, serializing the encoded digital data into encoded and serial digital data in a serializer, generating test data in a pseudo-random binary sequence generator circuit, transmitting the encoded and serial digital data through a multiplexer to a transmission medium in a normal mode of operation, and transmitting the test data through the multiplexer to the transmission medium in a test mode of operation. The encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated chip. The test data includes data to generate colors in a visual image, and the encoded and serial digital data is received, deserialized, decoded, and displayed in a display unit.

Abstract: A sequential access memory (“SAM”) device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of bit-lines transfer each of the group of bytes into and out of the memory array, and a pre-charging unit is configured to pre-charge the plurality of bit-lines once per each transfer of one of the group of bytes into or out of one of the plurality of rows. The device operates by accessing a memory array in a SAM device by activating a selected row in the memory array, pre-charging a plurality of bit-lines that provide access to the memory array, and accessing the memory array before the plurality of bit-lines are pre-charged a second time.

Abstract: A method of and apparatus for monitoring and intervening in, in real time, a collaboration between a plurality of subjects comprising measuring indicia of physiological and cognitive states of each of the plurality of subjects, communicating the indicia to a monitoring computer system, with the monitoring computer system, comparing the indicia with one or more models of previous collaborative performance of one or more of the plurality of subjects, and with the monitoring computer system, employing the results of the comparison to communicate commands or suggestions to one or more of the plurality of subjects.

Abstract: A sequential access memory (“SAM”) device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of bit-lines transfer each of the group of bytes into and out of the memory array, and a pre-charging unit is configured to pre-charge the plurality of bit-lines once per each transfer of one of the group of bytes into or out of one of the plurality of rows. The device operates by accessing a memory array in a SAM device by activating a selected row in the memory array, pre-charging a plurality of bit-lines that provide access to the memory array, and accessing the memory array before the plurality of bit-lines are pre-charged a second time.

Abstract: A fuse sensing circuit includes a sense controller and a fuse state sensor. The sense controller includes a reference fuse and a reference sensor coupled to the reference fuse. The reference sensor generates a sample clock with a certain threshold transition characteristic in response to the assertion of a sense input by detecting a programming state of the reference fuse. The fuse state sensor includes a sample fuse, a fuse sensor coupled to the sample fuse, and a flip-flop. The sample fuse is configured to generate a data signal indicative of a programming state of the sample fuse when an enable input is asserted and the sense input is asserted. The flip-flop is configured to sample the data signal using the threshold transition characteristic on an assertion edge of the sample clock. The fuse sensing circuit may be included in an image sensor or an imaging system.

Abstract: A memory device comprising memory cells having volatile and non-volatile memory portions. The volatile memory portion of each cell includes circuitry for performing RAM functions while the non-volatile memory portion comprises circuitry defining pre-coded data. The memory device comprises a mechanism to operate an initialization sequence, which sets the initial state of the volatile memory portion of each memory cell to the pre-coded data defined in the associated non-volatile memory portion. The initialization sequence allows the initial state of each memory cell's volatile portion to be re-established after power has been applied to the memory device.

Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

Abstract: A sequential access memory (“SAM”) device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of bit-lines transfer each of the group of bytes into and out of the memory array, and a pre-charging unit is configured to pre-charge the plurality of bit-lines once per each transfer of one of the group of bytes into or out of one of the plurality of rows. The device operates by accessing a memory array in a SAM device by activating a selected row in the memory array, pre-charging a plurality of bit-lines that provide access to the memory array, and accessing the memory array before the plurality of bit-lines are pre-charged a second time.

Abstract: A sequential access memory (“SAM”) device, system and method is provided that includes a memory array configured to store a group of bytes on each of a plurality of rows. A plurality of bit-lines transfer each of the group of bytes into and out of the memory array, and a pre-charging unit is configured to pre-charge the plurality of bit-lines once per each transfer of one of the group of bytes into or out of one of the plurality of rows. The device operates by accessing a memory array in a SAM device by activating a selected row in the memory array, pre-charging a plurality of bit-lines that provide access to the memory array, and accessing the memory array before the plurality of bit-lines are pre-charged a second time.

Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

Abstract: A fuse sensing circuit includes a sense controller and a fuse state sensor. The sense controller includes a reference fuse and a reference sensor coupled to the reference fuse. The reference sensor generates a sample clock with a certain threshold transition characteristic in response to the assertion of a sense input by detecting a programming state of the reference fuse. The fuse state sensor includes a sample fuse, a fuse sensor coupled to the sample fuse, and a flip-flop. The sample fuse is configured to generate a data signal indicative of a programming state of the sample fuse when an enable input is asserted and the sense input is asserted. The flip-flop is configured to sample the data signal using the threshold transition characteristic on an assertion edge of the sample clock. The fuse sensing circuit may be included in an image sensor or an imaging system.

Abstract: A memory device comprising memory cells having volatile and non-volatile memory portions. The volatile memory portion of each cell includes circuitry for performing RAM functions while the non-volatile memory portion comprises circuitry defining pre-coded data. The memory device comprises a mechanism to operate an initialization sequence, which sets the initial state of the volatile memory portion of each memory cell to the pre-coded data defined in the associated non-volatile memory portion. The initialization sequence allows the initial state of each memory cell's volatile portion to be re-established after power has been applied to the memory device.

Abstract: An embodiment includes encoding digital data into encoded digital data in a transition minimized differential signaling encoder, serializing the encoded digital data into encoded and serial digital data in a serializer, generating test data in a pseudo-random binary sequence generator circuit, transmitting the encoded and serial digital data through a multiplexer to a transmission medium in a normal mode of operation, and transmitting the test data through the multiplexer to the transmission medium in a test mode of operation. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The test data may be pseudo-random binary sequence data. The digital data may include data to generate colors in a visual image, and the encoded and serial digital data may be received, deserialized, decoded, and displayed in a display unit.

Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

Abstract: An adaptive threshold logic circuit is provided in which the switching threshold levels of the logic circuit are automatically changed to accommodate variations in the level of applied data signals to the switching circuit. A detector stage detects the voltage level of the incoming data signals and selectively adjusts the threshold level of a threshold adaptor stage in accordance with the output of the detector stage. The threshold adaptor stage is essentially an adaptive CMOS inverter having various switching paths turned on or off in accordance with the output of the detector stage.

Abstract: An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

Abstract: An embodiment includes encoding digital data into encoded digital data in a transition minimized differential signaling encoder, serializing the encoded digital data into encoded and serial digital data in a serializer, generating test data in a pseudo-random binary sequence generator circuit, transmitting the encoded and serial digital data through a multiplexer to a transmission medium in a normal mode of operation, and transmitting the test data through the multiplexer to the transmission medium in a test mode of operation. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The test data may be pseudo-random binary sequence data. The digital data may include data to generate colors in a visual image, and the encoded and serial digital data may be received, deserialized, decoded, and displayed in a display unit.