Abstract: A system and method is disclosed for reducing network message passing latency in a distributed multiprocessing computer system that contains a plurality of microprocessors in a computer network, each microprocessor including router logic to route message packets prioritized in importance by the type of message packet, age of the message packet, and the source of the message packet. The microprocessors each include a plurality of network input ports connected to corresponding local arbiters in the router. The local arbiters are each able to select a message packet from the message packets waiting at the associated network input port. Microprocessor input ports and microprocessor output ports in the microprocessor allow the exchange of message packets between hardware functional units in the microprocessor and between the microprocessors. The microprocessor input ports are similarly each coupled to corresponding local arbiters in the router.

Abstract: A real-time load-balancing system for distributing a sequence of incoming data packets emanating from a high speed communication line to a plurality of processing means, each operating at a capacity that is lower than the capacity of the high speed communication line; the system according to the invention comprises: a parser capable of extracting a configurable set of classifier bits from the incoming packets for feeding into a compression means; the compression means is capable of reducing a bit pattern of length K to a bit pattern having a length L which is a fraction of K; a pipeline block for delaying incoming packets until a load balancing decision is found, and an inverse demultiplexer for receiving a port identifier output from said compression means as selector and for directing pipelined packets to the appropriate output port.

Abstract: A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to processors in the clusters. Upon receiving an exclusive request from a processor requesting permission to modify a shared copy of the data, the directory controller generates invalidate messages requesting that other processors sharing the same data invalidate that data. These invalidate messages are sent via a point-to-point transmission only to master processors in clusters actually containing a shared copy of the data. Upon receiving the invalidate message, the master processors broadcast the invalidate message in an ordered fan-in/fan-out process to each processor in the cluster.

Abstract: A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system.

Abstract: A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to processors in the clusters. Upon receiving an exclusive request from a processor requesting permission to modify a shared copy of the data, the directory controller generates invalidate messages requesting that other processors sharing the same data invalidate that data. These invalidate messages are sent via a point-to-point transmission only to master processors in clusters actually containing a shared copy of the data. Upon receiving the invalidate message, the master processors broadcast the invalidate message in an ordered fan-in/fan-out process to each processor in the cluster.

Abstract: A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices are coupled to the I/O bridge ASIC, each I/O device capable of accessing machine resources in the computer system by transmitting and receiving message packets. Machine resources in the computer system include data blocks, registers and interrupt queues. Each processor in the computer system is coupled to a memory module capable of storing data blocks shared between the processors. Coherence of the shared data blocks in this shared memory system is maintained using a directory based coherence protocol. Coherence of data blocks transferred during I/O device read and write accesses is maintained using the same coherence protocol as for the memory system.

Abstract: The electrically adjustable phase-shifting device is arranged on a substrate comprising at least a first waveguide designed for guiding optical signals and a thermoelectric element arranged adjacent to the first waveguide in order to shift the phase of an optical signal in the first waveguide by means of a thermo-optic effect according to a control voltage applied to the thermo-electric element. According to the present invention the thermo-electric element is a Peltier element which comprises at least a first and a second electrically conducting segment which are serially connected, the first and the second element alternating consecutively, with the even numbered junctions of the electrically conducting segments forming one thermal side and the odd numbered junctions of the electrically conducting segments forming the other thermal side of the thermoelectric element.

Abstract: A switch for use in an ATM network is disclosed. The switch is designed to perform a function beyond that normally achievable with a virtual path switch functioning in accordance with the ATM standard. The switch according to the invention has data stored in a look-up table (431-433) which allows it to identify communication cells of particular individual virtual channels, indicated by the virtual path identifier (VCI), although these cells cannot be distinguished on the basis of their virtual path indicators (VPIs). This identification is attempted before the usual step of forwarding an incoming communication cell based solely on its virtual path indicator. A priority circuitry (44) ensures that entries associated with the combined VPI/VCI is given a priority over those associated only with the VPI. The switch can extract cells of individual virtual channels passing through it. It can also insert virtual channels into the ATM network.

Abstract: Optoelectronic composite consisting of two chips, the first chip 10 being made of a first material, the second one 13 being made of another material. The first chip 10, for example, comprises a multiplicity of active optoelectronic devices e.g. a laser diode 11 and a photo diode 12, all being monolithically integrated. A multiplicity of other optical devices, e.g. a waveguide 16, is monolithically integrated on the second chip 13. In addition this second chip 13 has depressions of the size of the devices 11,12 integrated on said first chip 10. These devices and the waveguide 16 of the second chip 13 are automatically aligned when flipping both chips together.

Abstract: Automatic alignment of an optical waveguide to a ridge waveguide laser is accomplished by transferring the ridge structure of the laser to a substrate by etching a mirror groove. The transferred ridge structure serves as a base for the deposition of waveguide layers. The thickness of the waveguide layers are controlled during the deposition such that the waveguide core is laterally and vertically aligned to the lasing active layer of the laser structure.

Abstract: A method for insuring data consistency between a plurality of individual processor cache memories and the main memory in a multi-processor computer system is provided which is capable of (1) detecting when one of a set of predefined data inconsistency states occurs as a data transaction request is being processed, and (2) correcting the data inconsistency states so that the operation may be executed in a correct and consistent manner.

Abstract: A method of passivating etched mirror facets of semiconductor laser diodes which enhances device reliability.The etched mirror facet is first subjected to a weet-etch process to substantially remove any native oxide as well as any surface layer which may have been mechanically damaged during the preceding mirror etch process. Then, a passivation pre-treatment is applied whereby any residual oxygen is removed and a sub-monolayer is formed which permanently reduces the non-radiative recombination of minority carriers at the mirror facet. Finally, the pre-treated mirror surface is coated with a passivation layer to avoid any environmental effect on the mirror.

Abstract: A method, and device produced therewith, for improving the planarity of etched mirror facets 18 of integrated optic structures with non-planar stripe waveguides, such as ridge or groove diode lasers or passive devices such as modulators and switches. The curvature of the mirror facet surface at the edges of the waveguide due to topographical, lithographical and etch process effects, causes detrimental phase distortions, and is avoided by widening the waveguide end near the mirror surface thereby shifting the curved facet regions away from the light mode region to surface regions where curvature is not critical.

Abstract: A process for forming the ridge structure of a self-aligned InP-system, double heterostructure (DH) laser, particularly useful for long wavelength devices as required for signal transmission systems includes a thin Si.sub.3 N.sub.4 layer (41) inserted between a photoresist mask (42) that defines the ridge structure, and a contact layer (35). Using a Si.sub.3 N.sub.4 layer (4) deposited at a high plasma excitation frequency (RF) for adhesion promotion, and a low frequency deposited (LF) Si.sub.3 N.sub.4 layer (43) for device embedding, provides for the etch selectively required in the process step that is used to expose the contact layer to ohmic contact metallization deposition.

Abstract: A method, and device produced therewith, for improving the planarity of etched mirror facets 18 of integrated optic structures with non-planar stripe waveguides, such as ridge or groove diode lasers or passive devices such as modulators and switches. The curvature of the mirror facet surface at the edges of the waveguide due to topographical, lithographical and etch process effects, causes detrimental phase distortions, and is avoided by widening the waveguide end near the mirror surface thereby shifting the curved facet regions away from the light mode region to surface regions where curvature is not critical.

Abstract: A method and apparatus for maintaining orientation of a wafer with respect to the wafer holder and a source emission is disclosed.Briefly stated, a wafer is disposed on a wafer holder and displaced in translation only while made to continuously follow a planar closed path which allows the rotation of the wafer with respect to source of emission while keeping the wafer and the wafer holder uniformly aligned with respect to each other.

Abstract: A brake comprises a base on which a pair of brake shoes are mounted, springs to resiliently bias the brake shoes into engagement with a drum which is fixed relative to a rotatable member to be braked, to apply the brake, an electromagnet to move the brake shoes against the springs to release the brake, the electromagnet comprising a coil and an armature movable relative to the coil when the coil is energized, and a lost motion device automatically to maintain the movement of the armature relative to the coil within a predetermined range of movement irrespective of the amount of wear of the brake shoes.

Abstract: A high speed high contrast electron resist composition comprising a copolymer of polymethylmethacrylate/methacrylic acid having incorporated therein a metal selected from the group consisting of lead, barium, calcium and strontium is disclosed. The metal is present in the range of from about 0.001% to about 10% by weight of the copolymer.