Abstract: In one embodiment, a decompression circuit is provided for a data stream that includes code words representing compressed data and uncompressed data. The decompression circuit includes a translation circuit adapted to identify the code words in the data stream and to translate the identified code words into corresponding decompressed data words; and a shift register operable to serially shift in uncompressed data in the data stream and to shift in parallel the decompressed data words from the translation circuit.

Abstract: A read operation and a write operation are synchronized via one port of a memory cell to avoid contention between such operations while doubling the bandwidth of such operations. Data is read from and data is written to a memory cell through a single port of the cell. A memory cell having a port is provided, and a clock signal is also provided for clocking the memory cell. The clock signal has a leading edge and a lagging edge within a clock signal cycle. During a single clock cycle, an enable read control signal is asserted in response to the clock signal, and an enable write control signal is asserted in response to the clock signal. In response to the enable read control signal, read data stored within the memory cell is read through a port of the cell. In response to the enable write control signal, write data is written to the memory cell through the port.

Abstract: A method and apparatus are used to generate FFT data addresses based upon a computation stage value and a computation step value within that computation stage. The method includes the steps of generating a first data address by insertion at a bit insertion position a first bit between existing bits of a binary word and generating a second data address by inserting at the bit insertion position a second bit between existing bits of the binary word, wherein the binary word represents the computation step value. The apparatus includes a series of consecutive bit cells that generate the desired data addresses based upon a decoded value of the computation stage.

Abstract: An apparatus and method for detecting the presence of a display device at the output of a video driver utilizes a terminating resistance connected between the output of the video driver and a ground level. A current is driven by the video driver, resulting in a voltage level at the output. A comparator compares the resultant voltage to a reference voltage signal to determine whether the resultant voltage is above or below a predefined threshold. The threshold is chosen as lying between an anticipated resultant voltage for a video driver having a display device connected thereto and an anticipated resultant voltage for a video driver without a display device connected thereto.

Abstract: An apparatus and method for converting pixel data from a computer video format to a television-compatible composite video waveform. A color space converter converts RGB or YCrCb pixel data into YUV pixel data. The YUV pixel data is supplied to an encoder which encodes the data into a composite video waveform. A clock generator generates an encoder clock frequency based on the horizontal resolution of the incoming computer pixel data. The encoder clock frequency is sufficient to allow encoding of all incoming pixels in the active video portion of the waveform without physically scaling or altering the pixel data. Sync and burst processors in the encoder encode sync pulses and burst waveforms at proper timing intervals despite the variable encoder clock frequency by accessing sync pulse and burst waveform values and timing parameters appropriate to ranges of clock frequencies that are stored in a ROM.

Abstract: An apparatus and method for detecting the presence of a display device at the output of a video driver utilizes a terminating resistance connected between the output of the video driver and a ground level. A current is driven by the video driver, resulting in a voltage level at the output. A comparator compares the resultant voltage to a reference voltage signal to determine whether the resultant voltage is above or below a predefined threshold. The threshold is chosen as lying between an anticipated resultant voltage for a video driver having a display device connected thereto and an anticipated resultant voltage for a video driver without a display device connected thereto.

Abstract: Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the sync pulse, and an adjacent one of system adjacent clock signals at a particular frequency. The actual or expected phase adjustment between the pixels at the end of each line is also determined. The difference between the phase adjustments at the beginning and end of each line is then determined. Progressive adjustments are made in the phase of each successive pixel in the line relative to the system clock signals in accordance with the number of system clock signals in the line and the determined difference in the phase adjustment between the line beginning and end. In this way, the pixels of video data are synchronized with the system clock signals.

Abstract: Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the sync pulse, and an adjacent one of system adjacent clock signals at a particular frequency. The actual or expected phase adjustment between the pixels at the end of each line is also determined. The difference between the phase adjustments at the beginning and end of each line is then determined. Progressive adjustments are made in the phase of each successive pixel in the line relative to the system clock signals in accordance with the number of system clock signals in the line and the determined difference in the phase adjustment between the line beginning and end. In this way, the pixels of video data are synchronized with the system clock signals.

Abstract: A system converts PAL and NTSC pixel clock signals to signals (in a studio, digital or square pixel format) at a sub-carrier frequency individual to the PAL and NTSC formats. The system includes a first register for providing a particular increase in the register count upon each occurrence of a pixel clock signal. Any remainder in the first register upon the production of the output signal is introduced to the register upon the occurrence of the next pixel clock signal. The particular increase in the first register count is controlled by a value in a second register, this value being adjustable dependent upon the system format and mode. A sequence of registers may be substituted for the first register with each register receiving an output from the previous register in the sequence. The system also converts signals representing the primary colors to luminance and chrominance signals.